1. 1 FINAL PRESENTATION PART A Implementation of generic interface To electronic components via USB2 Connection Supervisor Daniel Alkalay System architectures Roee Cohen Rami May Technion – Israel Institute of Technology Department of Electrical Engineering High-Speed Digital Systems Lab 1

2. 2 AGENDA Project Goals System Architecture System Micro- Architecture GUI Block Diagram - Controlling A/D Future targets Schedule 2

3. 3 Project Goal Development and implementation of generic interface system between PC via USB2 and electronic components Software/hardware integration has never been so easy 3

4. 4 System Architecture FPGA D/A (T.I) Analog signal USB2 100Mhz A/D (T.I) Electronic component PCB card Function generator 4

5. 5 System Micro-Architecture FPGA 50Mhz GUI The major elements that will be design & implemented 5

6. 6 System Micro-Architecture GUI GUI 16

7. 7 FPGA-USB2.0 CONTROL PANEL ABOUT USHELPEXIT DRR DANNY-RAMI-ROEE HARDARE AND SOFWARE CORPORATIONS GENERIC INTERFACE TO ELECTRONIC COMPONENTS VIA USB2 CONNECTION CONTINUE 18

8. 8 FPGA-USB2.0 CONTROL PANEL MAIN MENU: What do you want to do ? 1.Get the FPGA status. 2. Get registers values. 3.Get the board status. 4.Operate board peripherals. 5.Operate A/D 6.Help 7.Exit 19

9. 9 FPGA-USB2.0 CONTROL PANEL FPGA status : CONNECTED: CONFIG DONE: WORKING WITH A/D: WORKING WITH PCB1: 19

10. 10 FPGA-USB2.0 CONTROL PANEL Registers Values: 19 valueRegister address 0x12340x0000 0xC0FE0x0001 0xABBA0x0010 0xC0BA0x0011 0xB0CA0x0100 0x0F160x0101 …0x0110 …0x0111 0x1000 0x1001 0x1010 0x1011 0x1100 0x1101 0x1110 0x1111

11. 11 FPGA-USB2.0 CONTROL PANEL Board status. LED’S: SEGMENTS DISPLAY: 19 7 6 5 4 3 2 1 0 0x5A

12. 12 FPGA-USB2.0 CONTROL PANEL Operate Board Peripherals. Please enter your choice : LED’S: 1.Switch led 0. 2. Switch led 1. 3. Switch led 2. 4. Switch led 3. 5. Switch led 4. 6. Switch led 5. 7. Switch led 6. 8. Switch led 7. 9. reset all led’s SEGMENTS DISPLAY: 9.Set value 10.Up 11.Down 12.Reset segments. 19

13. 13 FPGA-USB2.0 CONTROL PANEL Operate A/D : 1. Enter the path of destination file. 2. Start operation of A/D. 19 ANALOG SIGNAL A/DFPGA

14. 14 GUI : user interface functions: provides an effective way to communicate with board : Operate state machines. Transfer and receive of data. Get current status of FPGA and Board Configure on-board peripherals. GUI SOFTWARE FPGA 22

15. 15 Interface with A/D FPGA 23

16. 16 Interface to A/D PC - command Operate A/d Cypress SPI flash Parsing protocol Activate operation command to A/D Perform Configuration of A/D Transfer samples to Cypress Read & Store Display data on PC screen 24

17. 17 Configuration stages 1-4 IDLE Wait for “data_av” From A/D Read from A/D Push samples to FIFO FIFO If (Num of samples > 256) IDLE Transfer Data to CYPRESS Read data from FIFO If (FIFO empty) State-machine for configuration read & store data State-machine for transferring data Block Diagram - Controlling A/D 25

18. 18 Future targets: FPGA 26 1.Implementation of GUI (software ). 2.Physical connection to A/D and get stream on data from it.

19. 19 Future schedule: Acquire all the hardware elementsWeek 1: creating a connection FPGA  A/D ( power supply, logic analyzer scope, function generator) Week 2-3: Full operation with A/D : PC USB cypress FPGA A/D Week 4-6: Debugging and Simulation A/DWeeks 7-9 : Design and implementation of the GUIWeeks 10-13: Final PresentationWeeks 14: FPGA 26