1. Overview of Computer Architecture and Organization
Module I
Overview of Computer Architecture and Organization

2. Bus Interconnection
A bus is a communication pathway connecting two or more devices
It is a shared transmission medium
It consist of multiple lines each capable of transmitting binary 0 or 1
Bus that connects major components of computer is called System Bus

3. Bus Structure
A system bus contains lines with each line is assigned a function
3 functional groups :
Data
Address
Control
There is power distribution line to supply power

4. Bus Structure

5. Data lines Address Lines
Provides path for moving data among modules
Collectively called data bus
No. of lines is width of data bus
Address Lines
Used to designate source or destination of data
Used to address I/O ports

6. Control lines
Used to control access to and the use of address and data lines
They transmit:
Timing Signals: Indicate the validity of address and data
Control Signals: Specify operations to be performed

7. Typical Control lines
Memory Write : causes data on bus to be written to a specified memory location
Memory Read : causes data from addressed location to be placed on bus
I/O Write: causes data on the bus to be placed on addressed I/O port
I/O Read: causes data from the addressed I/O port to be placed on bus

8. Typical Control lines
Transfer ACK : Indicates data have been accepted from or placed on the bus
Bus Request: Indicates a module needs control of the bus
Bus Grant: Indicates bus request is granted
Interrupt Request : Indicates that an interrupt request is pending
Interrupt Acknowledge: Indicates that the pending interrupt request is recognised

9. Typical Control lines Clock: It is used to synchronize operations
Reset: It initializes all modules

10. Operation of Bus To send data To receive data Obtain the use of bus
Transfer data via bus
To receive data
Transfer a request for data
Wait for data from other module

11. Physical Realization of a Bus Architecture
System bus is a number of parallel electrical conductors (metal lines etched in a card) and each of system components taps into bus lines.

12. Physical Realization of a Bus Architecture

13. Multiple Bus Hierarchies
Why?
The more the devices connected, the greater the propagation delay hence less performance
Performance can be improved by increasing data rate and using wider databus
Two Approaches :
Traditional Bus Architecture
High Performance Architecture

14. Traditional Bus Architecture
Isolates processor to memory traffic from I/O traffic.
Cache Memory act as an interface to system bus
Expansion bus interfaces it to external devices

15. Traditional Bus Architecture

16. Traditional Bus Architecture
1. Local bus connects cache memory and support one or more local devices
2. Cache is attached to main memory,isolates main memory and Processor

17. Traditional Bus Architecture
3. Expansion Bus interface buffers data transfers between system bus and I/O controllers

18. Traditional Bus Architecture
4. Some examples of I/O devices attached:
Network : Local Area Network(LAN) (10 Mbps)
Modem : To connect to Wide Area Network(WAN)
Small Computer System Interface (SCSI): To support local disk drives and peripherals
Serial Port : for printer and Scanner

19. SCSI

20. Fire Wire

21. High Performance Architecture
As I/O performance increased, a high speed architecture named mezzanine architecture is used
A high speed bus is integrated to bring high speed devices closer to processor.

22. High Performance Architecture

23. High Performance Architecture
1) Local bus connects processor to cache controller which is connected to main memory via system bus

24. High Performance Architecture
1) Cache controller is integrated to a bridge (buffering device) that connects high speed bus
2) High Speed Bus connects to
High Speed LANs (100 Mbps)
Video and Graphic Workstation controllers
Interface Controllers to local peripheral buses-SCSI and Firewire

25. High Performance Architecture
Lower Speed devices are supported with an expansion bus with an interface buffering traffic between the expansion bus and the high speed bus.

26. Advantages
High Speed Bus brings high demand devices close to processor but independent.
Differences in the speed is tolerated
Changes in processor architecture does not affect high speed bus and vice versa

27. Elements of Bus Design The parameters that classify buses are
Bus Types
Method of Arbitration
Timing
Bus Width
Data Transfer Type

28. Bus Types Dedicated and Multiplexed Dedicated
Bus line is permanently assigned to a function or a subset of computer components
It uses multiple buses
Adv: High throughput and less bus contention
Disadv: increased size and cost

29. Bus Types Multiplexed: Same bus is used for different functions
E.g. Address and data may be transmitted over same set of lines
Adv: use of few lines saves space and cost
Disadv: complex circuitry is needed and less performance

30. Bus Types Physically Dedicated:
Multiple buses for a subset of modules.
e.g : All I/O Modules thru I/O Adapter
Adv: High throughput because of less contention
Disadv: Increased size and cost of system.

31. Method of Arbitration Centralized and Distributed Centralized :
A single hardware called bus controller allocates time on bus
Distributed :
Each module contains access control logic and modules act together to share the bus

32. Timing Synchronous and Asynchronous Synchronous:
Occurrence of events are controlled by clock
All events start at the beginning of clock cycle
Adv: Simple to implement and test
Disadv: less flexible – cannot take advantage of device performance

33. Synchronous

34. Timing
Asynchronous:
Occurrence of one event on bus follows the occurrence of previous event
Adv: fast and slow device can share the bus
Disadv: Difficult to implement

35. Asynchronous : Read

36. Asynchronous : Write

37. Bus Width Address Bus and Data Bus Address Bus: Data Bus
Wider address bus  greater range of locations
Data Bus
Wider data bus  greater number of bits per unit time

38. Data Transfer Type

39. Multiplexed Address/Data Bus

40. Dedicated Address/Data Bus

41. Read Modify Write Read followed by immediate write to the same address
Used to protect shared memory resources

42. Read After Write Write is immediately followed by Read
It is for checking purpose

43. Block Data Transfer
One address cycle is followed by n data cycles

44. End of Module I