1 GPS Waypoint Navigation Team M-2: Charles Norman (M2-1) Julio Segundo (M2-2) Nan Li (M2-3) Shanshan Ma (M2-4) Design Manager: Zack Menegakis Presentation 12: Short Final Presentation April 26, 2006 Overall Project Objective: Design a low-power chip that navigates an aircraft to pre- determined waypoints.
2 Status Design Proposal Design Proposal Architecture Proposal Architecture Proposal Size Estimates / Floorplan Size Estimates / Floorplan Gate-Level Design Gate-Level Design Spice Simulations (Schematic & Layout) Power Power Delays Delays Functional Block Verification Functional Block Verification Timing Verification Layout (DRC & LVS) Layout (DRC & LVS) Functional Blocks Functional Blocks Global (99%) Global (99%) By: Charles
3 Marketing What is a GPS Waypoint Navigator? –Uses & Applications Hardware VS Software –Very low-power –Compact ~ 2 Slides By: Charles
4 Design Process Description Requirements Math High-Level Simulations Behavioral Verilog Structural Verilog Schematics Layout ~ 5 Slides By: Nan
5 Algorithm Description Brief overview – – How it works? Clock Breakdown – –Why so many??? System Flow – –System Inputs Blackbox Outputs Blackbox Inputs SystemOutputs ~ 15 Slides By: Shanshan / Julio
6 Verification MATLAB Behavior Verilog Structural Verilog Schematics –Begin timing verification & serialization Layout Timing (post layout) ~ 10 Slides By: Julio
7 Floorplan Evolution Original Floorplans –Description –Why were they modified/scrapped? Latest Floorplan –Description –Why is it acceptable? ~ 5 Slides By: Shanshan
8 Layout Layer Masks Full chip layout Full chip layout w/ overlaid floorplan ~ 8 Slides By: Nan
9 Issues & Solutions Grouping & Re-grouping Initial I/O count > 200 Serialization Architecture Complexity –Trade off between I/O pins & accuracy –1 ft. Accuracy 4 Clocks –Chip Interface (i.e. unit conversions) –Blackbox or no Blackbox??? Overall Design Size –Transistor Count –Bus Sizes / Buffers –ECE File Space Power Simulations Cadence ~ 3 Slides By: Charles
10 Specifcations Pin Specs Circuit Specs –Transistor Counts –Area –Density Delays –Why they don’t mean anything??? Power ~ 3 Slides By: Charles
11 Conclusion By: Charles ~ 1 Slide
12 Updates Layout 99% done as of 8:59:59am this morning Finished analog sims for all functional blocks Cadence limits our top-level testing capabilities
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14 Questions Total # Slides ~ 54 Slides