Team W1 Design Manager: Rebecca Miller 1. Bobby Colyer (W11) 2. Jeffrey Kuo (W12) 3. Myron Kwai (W13) 4. Shirlene Lim (W14) Stage III: February 11 h 2004 GATE LEVEL DESIGN Presentation #4: Rijndael Encryption Overall Project Objective: Implement the new AES Rijndael algorithm on chip Integrated Circuit Design Project

Status  Design Proposal  Architecture Proposal  Size Estimates/Floorplan  Gate Level Design  Schematic Design (needs to be changed)  Layout (10% done)  To be Done  Simulations/Optimizations  Everything else… Integrated Circuit Design Project This will be the focus today!

Design Decisions & Problems DECISIONS Change Verilog to match new input control logic to SBOX Control Logic will be made of PMOS, can’t be done in Verilog Implemented clock divider using counters Propagate valid-in signal through dffs to obtain valid-out signal Added 3 rd SBOX oPROBLEMS Transistor Count is TOO big (~45k) Should we remove 5 rounds of permutations? (Most Likely) Should we remove the third SBOX? (Not Practical) Top Level Schematic simulations not done All blocks simulated and working Except output logic from SBOX (Demux logic) Integrated Circuit Design Project

FLOORPLAN Integrated Circuit Design Project

ADDED SBOX #3 -Previous design inefficient for small text -Makes Sense to Give Round Key Generation its own SBOX - But increased transistor count drastically to ~45k -The logic and muxes are HUGE Integrated Circuit Design Project

ELIMINATION - Eliminate 5 rounds - Eliminate 1 SBOX & control logic - Reduce transistor count to 27k Integrated Circuit Design Project

Clock Divider Add Round KeyDFFs for Valid Out Mux Tree In Mux Tree Out SBox Round Permutation and Pipe DFF Mux Tree In Mux Tree Out SBox Final Text Out Key Expand Mux Tree Out Mux Tree In SBox Round Permutation and Pipe DFF

module logicandsbox (Out, In); output [7:0] Out; input [7:0] In; reg[7:0]Out; case(In)// synopsys full_case parallel_case 8'h00: Out=8'h63; 8'h01: Out=8'h7c; 8'h02: Out=8'h77; 8'h03: Out=8'h7b; 8'h04: Out=8'hf2; 8'h05: Out=8'h6b; 8'h06: Out=8'h6f; 8'h07: Out=8'hc5; 8'h08: Out=8'h30; 8'h09: Out=8'h01; 8'h0a: Out=8'h67; 8'h0b: Out=8'h2b; 8'h0c: Out=8'hfe; 8'h0d: Out=8'hd7; 8'h0e: Out=8'hab; FUNCTIONAL MODEL OF ROM Case Statements Integrated Circuit Design Project

ROM Schematic Integrated Circuit Design Project

ROM Control with PMOS Integrated Circuit Design Project

Clock Divider Integrated Circuit Design Project

Key Expand Integrated Circuit Design Project

SBox Mux Tree In-Logic Integrated Circuit Design Project 8 x Mux5

SBox Mux Tree Out-Logic Integrated Circuit Design Project

Schematic Simulation Results e0 34 e7 8b Integrated Circuit Design Project

Metal Directionality Integrated Circuit Design Project

COMPONENTS AREA ESTIMATE ( um 2 ) Key Schedule  Registers & XORs 351 um x 70 um = 24,570 um 2 ROM  SBOX (2) 50 um x 170 um x 2 = 14,000 um 2  Control Logic (352 um x 70 um) – 14,000 um 2 = 10,640 um 2 Transformation  Register & XORs 160 um x 352 um = 56,320 um 2 Others  Buffers & Wiring 10% = 10,553 um 2 TOTAL 116,083 um 2 (~350 um x ~350 um) PREVIOUS AREA ESTIMATE

Previous Transistor Count (Assuming 32-bit Implementation)  XORs14,336  DFFs6,416  ANDs 120  SBOX2304  Muxes & Demuxes1074  Buffers (10%)2000 Total: 26, Integrated Circuit Design Project

Current PROBLEMATIC Transistor Count (Assuming 32-bit Implementation)  Clock Divider 165  Add Round Key 256  Valid Out DFFs (10) 266  SBoxMuxTreeIn (3) 7008  SBoxMuxTreeOut(3)  ROM (3) 7644  Key Expansion (10) 3840  Round Permutation (9)  Final Text Out 256 Total: Total with Buffer Estimate (10%) Changing the ROM Control to PMOS Integrated Circuit Design Project

Proposed Transistor Count Removing 3 rd SBox and Logic (Assuming 32-bit Implementation) Integrated Circuit Design Project  Clock Divider 165  Add Round Key 256  Valid Out DFFs (10) 266  SBoxMuxTreeIn (2) 4672  SBoxMuxTreeOut(2) 7984  ROM – Using PMOS Logic (2) 4888  Key Expansion (10) 3840  Round Permutation (9)  Final Text Out 256 Total: Total with Buffer Estimate (10%) 37985

Proposed Transistor Count with 5 Rounds of Encryption (Assuming 32-bit Implementation)  Clock Divider 165  Add Round Key 256  Valid Out DFFs (5) 136  SBoxMuxTreeIn (Text) 2336  SBoxMuxTreeIn (Key) 1056  SBoxMuxTreeOut (Text) 3992  SBoxMuxTreeOut (Key) 2038  ROM with New Control Logic (3) 7332  Key Expansion (5) 1920  Round Permutation (4) 5312  Final Text Out 256 Total: Total with Buffer Estimate (10%) Integrated Circuit Design Project

Alternative Implementations Transistor Count (Assuming 32-bit Implementation)  Current ~52,275  Minus 1 SBOX & Logic ~37,985  Minus 5 rounds & 1 SBOX and logic ~27, Integrated Circuit Design Project Problems: - Deciding between the three implementations - Security problems, transistor counts - Pipelining implementation given consideration

Questions? Answers??? Integrated Circuit Design Project