1. Noise Canceling in 1-D Data: Presentation #7 Seri Rahayu Abd Rauf Fatima Boujarwah Juan Chen Liyana Mohd Sharipp Arti Thumar M2 Feb 28 th, 2005 Functional Block Layout/Floorplan Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware Project Manager: Bobby Colyer

2. Status Design proposal (Done) Architecture proposal (Done) Size Estimates and Floorplan (Done) Gate Level Design - Schematics (Done) To be done: –Layout (35%) –Spice simulation

3. Design Decisions Successfully implemented Wallace + Booth Changed register design

4. Last week...

5. Updated Floorplan

6. Floating Point Adder (Vertical)

7. Floating Point Adder (Horizontal)

8. Wallace Tree (Before)

9. Wallace Tree + Booth Encoding

10. Barrel Shifter

11. Comparator

12. Add/Sub (FP Adder)

13. Register (16 bit)

14. Counter

15. Timing (FPA) Rise Time: 65 picoseconds(10%-90%) Fall Time: 56 ps

16. Updated Transistor Count Part Last Week’s Transistors New Transistors 16-bit FPA3x 4154 = 124623x 2746 = 8238 16-bit FPM3x 3858 = 115743x 4456 = 13368 Registers7x16x14 = 15687x 272 = 1904 ROM800783 Converter2x312 = 6242x 108 = 216 MUX384402 Adder248 Counter214222 Alternator640 Total ≈ 27938 + Misc ≈ 30000 ≈ 25381 + Misc ≈ 27000

17. Challenges… Finishing up layout Make sure that the signal strength is sufficient Need to decide (multiplier) – symmetry vs. trans count

18. Questions?