[M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Oct. 22 Overall Project Objective : Dynamic Control The Traffic Lights

Status  Design Proposal  Chip Architecture  Behavioral Verilog Implementation  Size estimates  Floorplanning  Behavioral Verilog simulated  Gate Level Design  Component Layout/Simulation  Chip Layout  Complete Simulation

Data Input Initial Values Clock Operation T, Left-Turn Counter R, r, R_ L, r_ l Flow Control FSM Light Contro l FSM Selection

Current Version Wire routing on each block

Refined Floorplan

[New] Wire Pre-Decision on Block M2 & M3 & M4 Selection & Control Signal M1 & M2 Multipliers M1 & M2 Adder/Subtrator M1 & M2 Accumulator M1 & M2 & M3 & M4 11-bit Reg.+12-bit Reg. M1 & M2 Register M1 & M2 & M3 & M4 2:1 MUX Array (x110) M1 & M2 & M3 16:1,2:1 MUX/DEMUX Metal Layers That Have Been Used Block

Flow Control FSM

ALU Update  Some wiring errors causing functionality of multiplier to break  Need to figure out which wires are connected incorrectly  Small cadence issue  Only lets me put load capacitances on 8/10 outputs instead of all 10  Layout  Is one directional poly a requirement?  Version 2 will be out by Monday

Mult(load 5f F, broken)

Mirror Adder Schematic

Mirror Adder Layout(V1)

1bit DFF Register

Shift Register

Design Decision  For shift register which is minimum sized, the waveform is not perfect, but it is slightly acceptable. Should we give appropriate sizing for it to obtain good wave form? It would waste areas. Some trade off here.

MUX Design  We have two different schematics for it. Without KeeperWith Keeper

Design Decision  Circuit with keeper could avoid floating point problem. If we used keeper, the area would increase a lot  We plan use keeper in DEMUX, and do not use it in MUX. Because we have to hold the values in DEMUX, and we don’t need to keep value in MUX.

2:1 MUX

DEMUX

Tester for Light Control FSM Stimulus files are used to test different cases. Part of the cases for next stage combinational logic haven’t been tested. Too many cases 

Waveform for Encoder Only one line goes high at each stage. (hot-one coded)

Waveform for Output It shows the signals to traffic light. It also demonstrates that the light for pedestrians are blinking in the final stage.

Issues  We use 50ps as the transition time by assuming the previous stage are sized by setting FO4.  There are some hazards in a few lines. But the transition time for these are short. Not quite sure how could this happen.  May need to fix these hazards if possible  Future work: finish the simulation for sequential parts.

Question ?