EE 4271 VLSI Design, Fall 2011 CMOS Combinational Gate.

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Presentation transcript:

EE 4271 VLSI Design, Fall 2011 CMOS Combinational Gate

CMOS Combinational Circuits Implementation of logic gates and other structures using CMOS technology. Basic element: transistor 2 types of transistors: – n-channel (nMOS) and p-channel (pMOS) – Type depends on the semiconductor materials used to implement the transistor. – We want to model transistor behavior at the logic level in order to study the behavior of CMOS circuits  view pMOS and nMOS transistors as swithes. 15-Jun-15Combinational Logic PJF - 2

CMOS transistors as Switches 15-Jun-15Combinational Logic PJF terminals in CMOS transistors:   G: Gate   D: Drain   S: Source nMOS transistor/switch X=1 switch closes (ON) X=0 switch opens (OFF) pMOS transistor/switch X=1 switch opens (OFF) X=0 switch closes (ON)

Networks of Switches Use switches to create networks that represent CMOS logic circuits. To implement a function F, create a network s.t. there is a path through the network whenever F=1 and no path when F=0. Two basic structures: – Transistors in Series – Transistors in Parallel 15-Jun-15Combinational Logic PJF - 4

Transistors in Series/Parallel 15-Jun-15Combinational Logic PJF - 5 nMOS in ParallelnMOS in Series X Y a b X:X Y:Y a b pMOS in Series X Y a b X:X’ Y:Y’ a b Path between points a and b exists if both X and Y are 1  XY Path between points a and b exists if both X and Y are 0  X’Y’ Path between points a and b exists if either X or Y are 1  X+Y X Y b a X:XY:Y b a pMOS in Parallel X Y b a X:XY:Y b a Path between points a and b exists if either X or Y are 0  X’+Y’

Networks of Switches (cont.) In general: 1.nMOS in series is used to implement AND logic 2.pMOS in series is used to implement NOR logic 3.nMOS in parallel is used to implement OR logic 4.pMOS in parallel is used to implement NAND logic Observe that: – 1 is the complement of 4, and vice-versa – 2 is the complement of 3, and vice-versa 15-Jun-15Combinational Logic PJF - 6

CMOS Inverter 15-Jun-15Combinational Logic PJF - 7 X X’ F = X’ Logic symbol X X’ F = X’ +V+V GRD Transistor-level schematic Operation:   X=1  nMOS switch conducts (pMOS is open) and draws from GRD  F=0   X=0  pMOS switch conducts (nMOST is open) and draws from +V  F=1

Fully Complementary CMOS Networks Basic Gates 15-Jun-15Combinational Logic PJF - 8

Fully Complementary CMOS Complex Gates Given a function F: 1.First take the complement of F to form F’ 2.Implement F’ as an nMOS net and connect it to GRD (pull- down net) and F. 3.Find dual of F’, implement it as a pMOS net and connect it to +V (pull-up net) and F. 4.Connect switch inputs. 15-Jun-15Combinational Logic PJF - 9

Fully Complementary CMOS Networks Complex Gates - Example 15-Jun-15Combinational Logic PJF - 10 F’ = A’B’+A’C=A’(B’+C) F = (A+B)(A+C’)

CMOS Transmission Gate (TG) 15-Jun-15Combinational Logic PJF - 11

2-input MUX Using CMOS TGs 15-Jun-15Combinational Logic PJF - 12