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Faculty of Computer Science © 2006 CMPUT 229 Digital Logic From Switches to Memories.

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Presentation on theme: "Faculty of Computer Science © 2006 CMPUT 229 Digital Logic From Switches to Memories."— Presentation transcript:

1 Faculty of Computer Science © 2006 CMPUT 229 Digital Logic From Switches to Memories

2 © 2006 Department of Computing Science CMPUT 229 Reading Material  These slides are based on the Text by Patt and Patel: Introduction to Computing Systems: From Bits & Gates to C & Beyond.  The concepts covered here are presented in Chapter 2 of Alan Clements’ textbook.

3 © 2006 Department of Computing Science CMPUT 229 The Light Switch

4 © 2006 Department of Computing Science CMPUT 229 A N-MOS transistor A Metal-Oxide Semiconductor (MOS) transistor has three terminals. The Gate controls the flow of electrons between the two other terminals. In a N-type MOS transistor, electrons will flow when a voltage of 2.9 V is applied to the Gate (closed circuit). If 0.0 V is applied to the Gate no electrons will flow (open circuit). 2.9 Volt battery (power supply) Gate

5 © 2006 Department of Computing Science CMPUT 229 P-MOS Transistor The operation of a P-type MOS transistor, is the opposite of an N-MOS: - electrons will flow when a voltage of 0.0 V is applied to the Gate (closed circuit). - If 2.9 V is applied to the Gate no electrons will flow (open circuit). Gate #1 #2

6 © 2006 Department of Computing Science CMPUT 229 The NOT Gate Problem: Use two MOS transistors to implement the following logic circuit: NOT 2.9 Volts 0 Volts In Out Your NOT circuit should implement the following logic function:

7 © 2006 Department of Computing Science CMPUT 229 2.9V 0V 0 Volts 2.9 Volts 0V 2.9 Volts 0 Volts 2.9V The NOT Gate In 2.9 Volts 0 Volts Out XX’

8 © 2006 Department of Computing Science CMPUT 229 The NOR Gate A C B A= 0V C= 0V B=0V

9 © 2006 Department of Computing Science CMPUT 229 The NOR Gate A C B A= 0V C= 0V B=2.9V

10 © 2006 Department of Computing Science CMPUT 229 The NOR Gate A C B A= 2.9V C= 0V B= 0V

11 © 2006 Department of Computing Science CMPUT 229 The NOR Gate A C B A= 2.9V C= 0V B= 2.9V XYXY Z

12 © 2006 Department of Computing Science CMPUT 229 What Logic Function this Circuit Implements? A B C D This is an OR gate. ABAB C=A+B

13 © 2006 Department of Computing Science CMPUT 229 The AND Gate A B C D ABAB C=A·B

14 © 2006 Department of Computing Science CMPUT 229 Logic Functions ABAB C=A+B ABAB C=A·B

15 © 2006 Department of Computing Science CMPUT 229 Logic Functions INVERTER XX’ If X=0 then X’=1 If X=1 then X’=0 OR ABAB C=A+B If A=1 OR B=1 then C=1 otherwise C=0 ABAB C=A·B If A=1 AND B=1 then C=1 otherwise C=0 AND

16 © 2006 Department of Computing Science CMPUT 229 NOR and NAND Because these combination of gates are used often, there are special symbols to represent them: XYXY Z XYXY Z Z XYXY XYXY Z  

17 © 2006 Department of Computing Science CMPUT 229 First DeMorgan’s Law The complement of the OR is equal the AND of the complements. (X+Y)’ = X’Y’ XYXY Z Z Y X 

18 © 2006 Department of Computing Science CMPUT 229 Decoders –General decoder structure –Typically n inputs, 2 n outputs –2-to-4, 3-to-8, 4-to-16, etc.

19 © 2006 Department of Computing Science CMPUT 229 Decoders 3-to-8 Line Decoder y 0 = a’b’c’ y 1 = a’b’c y 2 = a’bc’ y 3 = a’bc y 4 = ab’c’ y 5 = ab’c y 6 = abc’ y 7 = abc a b c

20 © 2006 Department of Computing Science CMPUT 229 Binary 2-to-4 decoder Note “x” (don’t care) notation.

21 © 2006 Department of Computing Science CMPUT 229 2-to-4-decoder logic diagram

22 © 2006 Department of Computing Science CMPUT 229 Instruction Decoder Clements, pp. 86 COPYRIGHT 2006 OXFORD UNIVERSITY PRESS ALL RIGHTS RESERVED

23 © 2006 Department of Computing Science CMPUT 229 The 74138 3-to-8 Decoder Clements, pp. 86 COPYRIGHT 2006 OXFORD UNIVERSITY PRESS ALL RIGHTS RESERVED

24 © 2006 Department of Computing Science CMPUT 229 Multiplexer Clements, pp. 84 COPYRIGHT 2006 OXFORD UNIVERSITY PRESS ALL RIGHTS RESERVED

25 © 2006 Department of Computing Science CMPUT 229 Multiplexer Clements, pp. 85 COPYRIGHT 2006 OXFORD UNIVERSITY PRESS ALL RIGHTS RESERVED

26 © 2006 Department of Computing Science CMPUT 229 Multiplexers 4-to-1 MUX I0I0 I1I1 I2I2 I3I3 AB Z ABI3ABI3 A B’ I 2 A’ B I 1 A’ B’ I 0 Z

27 © 2006 Department of Computing Science CMPUT 229 Multiple 2-to-1 Multiplexers Clements, pp. 84 COPYRIGHT 2006 OXFORD UNIVERSITY PRESS ALL RIGHTS RESERVED

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