1. Introduction to CMOS EE2174 Digital Logic and Lab Dr. Shiyan Hu
Office: EERC 518
Introduction to
CMOS
Adapted and modified from Digital Integrated Circuits: A Design Perspective
by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.

2. Goal of this chapter Present intuitive understanding on CMOS Device
Interconnect
Inverter
Combinational Gate

3. Device

4. MOS Transistor Types and SymbolsG S
NMOS D G S
PMOS

5. Circuit Under Design

6. Circuit on the Chip
A transistor

7. The MOS (Metal-Oxide-Semiconductor) Transistor
Polysilicon
Aluminum

8. Simple View of A Transistor
A Switch! |V GS |
An MOS Transistor

9. Silicon Basics Transistors are built on a silicon substrate
EE141
Silicon Basics
Transistors are built on a silicon substrate
Silicon forms crystal lattice with bonds to four neighbors 9

10. Doped Silicon n-type p-type Silicon is a semiconductor
EE141
Doped Silicon
Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
extra electrons (doped Borons) – n-type
missing electrons (doped Arsenic/Phosphorus) more holes) – p-type
n-type
p-type 10

11. NMOS Transistor
Diffusion

12. NMOS - II
Refer to gate, source, drain and bulk voltages as Vg,Vs,Vd,Vb, respectively.
Vab=Va-Vb
Device is symmetric. Drain and source are distinguished electrically, i.e., Vd>Vs.
P regions have acceptor (Boron) impurities, i.e., many holes.
N regions have donor (Arsenic/Phosphorus) impurities, i.e., many electrons.
N+ and P+ are heavily doped N and P regions, respectively.

13. NMOS - III Gate oxide are insulators, usually, silicon dioxide.
Gate voltage modulates current between drain and source, how?

14. Enhancement NMOS

15. Enhancement NMOS - II
Does not conduct when Vgs=0, except that there is leakage current.
When Vgs is sufficiently large, electrons are induced in the channel, i.e., the device conducts. This Vgs is called threshold voltage.

16. Enhancement NMOS III
Positively Charged
Negatively Charged

17. Enhancement NMOS - IV
When Vgs is large enough, the upper part of the channel changes to N-type due to enhancement of electrons in it. This is referred to as inversion, and the channel is called n-channel.
The voltage at which inversion occurs is called the Threshold Voltage (Vt).
A p-depletion layer have more holes than p-substrate since its electrons have been pushed into the inversion layer.
Does not conduct when Vgs<Vt (Cut-off).

18. Enhancement NMOS V

19. Enhancement NMOS - VI
When Vgs>Vt, the inversion layer (n channel) becomes thicker.
The horizontal electrical field due to Vds moves electrons from the source to the drain through the channel.
If Vds=0, the channel is formed but not conduct.

20. Case when Vds=0

21. Linear Region

22. Linear Region - II
When Vgs>Vt and Vgd>Vt, the inversion layer increases in thickness and conduction increases.
The reason is that there are non-zero inversion layer at both source and drain (our previous analysis works for both Vgs and Vgd).This is called linear region.
Vgd>Vt means that Vgd=Vgs-Vds>=Vt, i.e., Vds<=Vgs-Vt
Vds>0
Ids depends on Vg, Vgs, Vds and Vt.

23. Saturation Region

24. Saturation Region - II
When Vgs>Vt and Vgd<Vt, we have non-zero inversion layer at source but zero inversion layer at drain.
Inversion layer is said to be pinched off. This is called the saturation region.
Vgd<Vt means that Vgs-Vds<Vt, i.e., Vds>Vgs-Vt.
Electrons leaves the channel and moves to drain terminal through depletion region.

25. Summary Three regions of conduction Cut-off: 0<Vgs<Vt
Linear: 0<Vds<Vgs-Vt
Saturation: 0<Vgs-Vt<Vds
Vt depends on gate and insulator materials, thickness of insulators and so forth – process dependant factors, and Vsb and temperature – operational factors.

26. PMOS

27. PMOS - II Dual of NMOS Three regions of conduction
Cut-off: 0>Vgs>Vt
Linear: 0>Vds>Vgs-Vt
Saturation: 0>Vgs-Vt>Vds
Current computation is the same as NMOS except that the polarities of all voltages and currents are reversed.
Mobility in PMOS is usually half of the mobility in NMOS due to process technology.

28. I-V characteristics (different Vt)

29. I-V Characteristics II

30. Wire

31. Modern Interconnect

32. Modern Interconnect - II

33. Interconnect Delay Dominates
300
250
200
Interconnect delay
150
Delay (psec)
100
Transistor/Gate delay 50 33
[CF] The problem is that at 0.18u and below interconnect overwhelmingly dominates the delay on a chip, and current design methods have been created to only consider the delay from the transistor gate. So, you never get a true timing picture of the performance of your chip during your design iterations. The impact of this is difficulty in achieving Design Closure. This is important because it will cause delay in the delivery of your chip and uncertainty in its performance.
[Michel] The above graphic shows how interconnect delay accounts for most of the delay in chips today and will continue to do so with advancing technologies. This is mainly due to the shrinking gate sizes which reduces the gate capacitance and the shrinking widths and spacing of the interconnect which increases the overall interconnect capacitance. Please turn to the next slide titled “and Coupling Dominates Interconnect”.
0.8
0.5
0.35
0.25
0.25
0.18
0.15
Technology generation (m)
Source: Gordon Moore, Chairman Emeritus, Intel Corp.

34. Capacitor
A capacitor is a device that can store an electric charge by applying a voltage
The capacitance is measured by the ratio of the charge stored to the applied voltage
Capacitance is measured in Farads

35. 3D Parasitic Capacitance
Given a set of conductors, compute the capacitance between all pairs of conductors. 1V + - - + + + - + -
C=Q/V - - -

36. Simplified Model
Area capacitance (Parallel plate): area overlap between adjacent layers/substrate
Fringing/coupling capacitance:
between side-walls on the same layer
between side-wall and adjacent layers/substrate m3 m2 m2 m2 m1

37. The Parallel Plate Model (Area Capacitance)
Capacitance is proportional to the overlap between the conductors and inversely proportional to their separation

38. Wire Capacitance
More difficult due to multiple layers, different dielectric m2 m1 m3
=3.9
=8.0
=4.0
=4.1
multiple
dielectric

39. Simple Estimation Methods
C = Ca*(overlap area)
+Cc*(length of parallel run)
+Cf*(perimeter)
Coefficients Ca, Cc and Cf are given by the fab
Cadence Dracula
Fast but inaccurate

40. Accurate Methods In Industry
Finite difference/finite element method
Most accurate, slowest
Raphael
Boundary element method
FastCap, Hicap

41. Wire Resistance Basic formula R=(/h)(l/w)  : resistivity l
h: thickness, fixed for a given technology and layer number
l: conductor length
w: conductor width l h w

42. Analysis of Simple RC Circuit
vT(t)
v(t) C
state variable
Input
waveform

43. Analysis of Simple RC Circuit
Step-input response: v0
v0u(t)
v0(1-e-t/RC)u(t)
match initial state:
output response for step-input:

44. 0.69RC v(t) = v0(1 - e-t/RC) -- waveform under step input v0u(t)
v(t)=0.5v0  t = 0.69RC
i.e., delay = 0.69RC (50% delay)
v(t)=0.1v0  t = 0.1RC
v(t)=0.9v0  t = 2.3RC
i.e., rise time = 2.2RC (if defined as time from 10% to 90% of Vdd)
Elmore Delay TD = 0.69 RC

45. Elmore Delay
50%-50% point delay
Delay=0.69RC
Delay

46. Delay

47. Elmore Delay - III
What is the delay of a wire?

48. Elmore Delay – IV Precisely, should be 0.69RC/2
Assume: Wire modeled by N equal-length segments
For large values of N:
Precisely, should be 0.69RC/2

49. Elmore Delay - V n2 n1 n1 n2 C/2 R R=unit wire resistance*length
C=unit wire capacitance*length

50. RC Tree Delay Unit wire cap=1, unit wire res=1 Precisely, 0.69*48.52 2 7 2 7
24+4*2=32 1 1
3.5
3.5 2
Unit wire cap=1, unit wire res=1
2*( )=24
24+7*3.5=48.5
Precisely, 0.69*48.5
RC Tree Delay=max{32,48.5}=48.5

51. Inverter

52. Circuit Symbols

53. The CMOS Inverter V in
out C L DD S D
Vin=Vdd,Vout=0
Vin=0,Vout=Vdd

54. Its Layout View

55. Pass-Transistors NMOS based PMOS based
Need a circuit element which acts as a switch
When the control signal CLK is high, Vout=Vin
When the control signal CLK is low, Vout is open circuited
We can use NMOS or PMOS to implement it. For PMOS device, the polarity of CLK is reversed.
NMOS based
PMOS based

56. NMOS Pass Transistors Initially Vout=0. input=drain, output=source
When CLK=0, then Vgs=0. NMOS cut-off
When CLK=Vdd,
If Vin=Vdd (Vout=0 initially), Vgs>Vt, Vgs-Vt=Vdd-Vt<=Vds=Vdd, NMOS is in saturation region as a transient response and CL is charged.
When Vout reaches Vdd-Vt, Vgs=Vdd-(Vdd-Vt)=Vt. NMOS cut-off.
However, if Vout drops below Vdd-Vt, NMOS will be turned on again since Vgs>Vt.
Thus, NMOS transmits Vdd value but drops it by Vt.

57. NMOS Pass Transistors - II
If Vin=0 (and CLK=Vdd), source=input, drain=output
If Vout=Vdd-Vt (note that it is the maximum
value for Vout for the transistor to be on), Vgs=Vdd>Vt, Vds=Vdd-Vt=Vgs-Vt
The NMOS is on the boundary of linear region and saturation region
CL is discharged
As Vout approaches 0, the NMOS is linear region. Thus, Vout is completely discharged.
When Vout=0, Vds=0 and Ids=0, thus, the discharge is done.
NMOS pass transistor transmits a 0 voltage without any degradation

58. PMOS Pass Transistors Similar to NMOS pass transistor
Assume that initially Vout=0
When CLK=Vdd, PMOS cut-off
When CLK=0,
If Vin=Vdd, PMOS transmits a Vdd value without degradation
If Vin=0, PMOS transmits a 0 value with degradation, Vout=|Vt|

59. Transmission Gate
An NMOS transmits a 0 value without degradation while transmits a Vdd value with degradation
A PMOS transmits a Vdd value without degradation while transmits a 0 value with degradation
Use both in parallel, then can transmit both 0 and Vdd well.
CLK=0, both transistors cut-off
CLK=Vdd, both transistors are on. When Vin=Vdd, NMOS cut-off when Vout=Vdd-Vtn, but PMOS will drag Vout to Vdd. When Vin=0, PMOS cut-off when Vout=|Vtp|, but NMOS will drag Vout to 0.

60. Power Dissipation

61. Where Does Power Go in CMOS?

62. Dynamic Power Dissipation
Vin
Vout C L
Vdd
Power = C
* V 2
* f L dd
Not a function of transistor sizes
Need to reduce C
, V
, and f
to reduce power. L dd

63. Dynamic Power
Dynamic power is due to charging/discharging load capacitor CL
In charging, CL is loaded with a charge CL Vdd which requires the energy of QVdd= CL Vdd2, and all the energy will be dissipated when discharging is done. Total power = CL Vdd2
If this is performed with frequency f, clearly, total power = CL Vdd2 f

64. Dynamic Power- II
If the waveform is not periodic, denote by P the probability of switching for the signal
The dynamic power is the most important power source
It is quadratically dependant on Vdd
It is proportional to the number of switching. We can slow down the clock not on the timing critical path to save power.
It is not dependent of the transistor itself but the load of the transistor.

65. Leakage Sub-threshold current one of most compelling issues
in low-energy circuit design.

66. Subthreshold Leakage Component

67. Principles for Power Reduction
Prime choice: Reduce voltage
Recent years have seen an acceleration in supply voltage reduction
Design at very low voltages still open question (0.5V)
Reduce switching activity
Reduce physical capacitance

68. Combinational Gate

69. CMOS Combinational Circuits
25-Apr-17
CMOS Combinational Circuits
Implementation of logic gates and other structures using CMOS technology.
Basic element: transistor
2 types of transistors:
n-channel (nMOS) and p-channel (pMOS)
Type depends on the semiconductor materials used to implement the transistor.
We want to model transistor behavior at the logic level in order to study the behavior of CMOS circuits  view pMOS and nMOS transistors as swithes.

70. 25-Apr-17
Networks of Switches
Use switches to create networks that represent CMOS logic circuits.
To implement a function F, create a network s.t. there is a path through the network whenever F=1 and no path when F=0.
Two basic structures
Transistors in Series
Transistors in Parallel

71. Transistors in Series/Parallel
25-Apr-17
Transistors in Series/Parallel
nMOS in Series
nMOS in Parallel a a
Path between points a and b exists if both X and Y are 1  X•Y a a
Path between points a and b exists if either X or Y are 1  X+Y X
X:X X Y
X:X
Y:Y Y
Y:Y b b b b
pMOS in Parallel
pMOS in Series a a a a
Path between points a and b exists if either X or Y are 0  X’+Y’
Path between points a and b exists if both X and Y are 0  X’•Y’ X
X:X’ X Y
X:X
Y:Y Y
Y:Y’ b b b b

72. Networks of Switches (cont.)
25-Apr-17
Networks of Switches (cont.)
In general:
nMOS in series is used to implement AND logic
pMOS in series is used to implement NOR logic
nMOS in parallel is used to implement OR logic
pMOS in parallel is used to implement NAND logic
Observe that:
1 is the complement of 4, and vice-versa
2 is the complement of 3, and vice-versa

73. Fully Complementary CMOS Networks Basic Gates
25-Apr-17
Fully Complementary CMOS Networks Basic Gates

74. Fully Complementary CMOS Complex Gates
25-Apr-17
Fully Complementary CMOS Complex Gates
Given a function F:
First take the complement of F to form F’
Implement F’ as an nMOS net and connect it to GRD (pull-down net) and F.
Find dual of F’, implement it as a pMOS net and connect it to +V (pull-up net) and F.
Connect switch inputs.

75. Fully Complementary CMOS Networks Complex Gates - Example
25-Apr-17
Fully Complementary CMOS Networks Complex Gates - Example
F = (A+B)(A+C’)
F’ = A’B’+A’C=A’(B’+C)