PCPC addr instr INSTR MEM R1 R2 WR W Data R Data 1 R Data 2 ALU DATA MEM ALU CTRL rs rt op +4 shift 2 zero BRANCH CTRL muxmux sign extend immed 1632 ADDADD ADDADD Single Cycle Datapath muxmux muxmux addr w data r data rd

PCPC addr REGISTERS MEMORY R1 R2 WR W Data R Data 1 R Data 2 ALU data ALU CTRL rs rt rd fctnopshamt Multicycle Datapath A B w data immedsign extend shift 2 +4 IRIR MRMR z alu out shift 2jump addr fetch decode execute (1..3)

PCPC addr REGISTERS MEMORY R1 R2 WR W Data R Data 1 R Data 2 ALU data CONTROL rs rt rd fctnopshamt Multicycle with Exception/Interrupt Handling A B w data immedsign extend shift 2 +4 IRIR MRMR zero alu out shift 2jump addr EPCEPC CAUSECAUSE PC - 4 handler addr to? overflow to?

Pipelined Datapath PCPC Instruction Memory addr out Registers read1 read2 write w data data1 data2 sign extend add +4 shift add ALUALU Data Memory addr w data r data muxmux muxmux muxmux IFIDEXMEMWB

add rd, rt, rs: Fetch PCPC Instruction Memory addr out Registers read1 read2 write w data data1 data2 sign extend add +4 shift add ALUALU Data Memory addr w data r data muxmux muxmux muxmux Instruction Fetch: Load IR, PC = PC + 4 IF Register Contains IR and PC, and other values

add rd, rt, rs: Decode PCPC Instruction Memory addr out Registers read1 read2 write w data data1 data2 sign extend add +4 shift add ALUALU Data Memory addr w data r data muxmux muxmux muxmux Instruction Decode: Load data1, data2 into A, B (part of ID) ID register contains A, B, and other values

add rd, rt, rs: Execute PCPC Instruction Memory addr out Registers read1 read2 write w data data1 data2 sign extend add +4 shift add ALUALU Data Memory addr w data r data muxmux muxmux muxmux Execute: sum of A, B into ALUout (part of EX)

add rd, rt, rs: MEM PCPC Instruction Memory addr out Registers read1 read2 write w data data1 data2 sign extend add +4 shift add ALUALU Data Memory addr w data r data muxmux muxmux muxmux MEM: (no memory access) save ALU result in MEM

add rd, rt, rs: WB PCPC Instruction Memory addr out Registers read1 read2 write w data data1 data2 sign extend add +4 shift add ALUALU Data Memory addr w data r data muxmux muxmux muxmux Write Back: write sum to register rd

sw rt, offset(rs): Fetch PCPC Instruction Memory addr out Registers read1 read2 write w data data1 data2 sign extend add +4 shift add ALUALU Data Memory addr w data r data muxmux muxmux muxmux

sw rt, offset(rs): Decode PCPC Instruction Memory addr out Registers read1 read2 write w data data1 data2 sign extend add +4 shift add ALUALU Data Memory addr w data r data muxmux muxmux muxmux ID gets rs, rt, and immed+sign ext

sw rt, offset(rs): Execute PCPC Instruction Memory addr out Registers read1 read2 write w data data1 data2 sign extend add +4 shift add ALUALU Data Memory addr w data r data muxmux muxmux muxmux EX gets rs+offset, and rt

sw rt, offset(rs): MEM PCPC Instruction Memory addr out Registers read1 read2 write w data data1 data2 sign extend add +4 shift add ALUALU Data Memory addr w data r data muxmux muxmux muxmux Write Data Memory [address] with rt value; nothing of interest in WD

sw rt, offset(rs): WB PCPC Instruction Memory addr out Registers read1 read2 write w data data1 data2 sign extend add +4 shift add ALUALU Data Memory addr w data r data muxmux muxmux muxmux Registers not written in this instruction

A program fragment with 6 instructions 1. add r1, r2, r3 2. sw r4, 2232 ( r5 ) 3. addi r6, lw r7, 1001 (r8) 5. bneq r7, r6, add r1, r7, r0

A program fragment with 6 instructions 1. add r1, r2, r3 2. sw r4, 2232 ( r5 ) 3. addi r6, lw r7, 1001 (r8) 5. slti r7, r6, add r1, r7, r0

Six instructions 1,2,3,4,5,6: Step 1 PCPC Instruction Memory addr out Registers read1 read2 write w data data1 data2 sign extend add +4 shift add ALUALU Data Memory addr w data r data muxmux muxmux muxmux Fetch 1

Six instructions 1,2,3,4,5,6: Step 2 PCPC Instruction Memory addr out Registers read1 read2 write w data data1 data2 sign extend add +4 shift add ALUALU Data Memory addr w data r data muxmux muxmux muxmux Fetch 2Decode 1

Six instructions 1,2,3,4,5,6: Step 3 PCPC Instruction Memory addr out Registers read1 read2 write w data data1 data2 sign extend add +4 shift add ALUALU Data Memory addr w data r data muxmux muxmux muxmux Fetch 3 Decode 2 Execute 1

Six instructions 1,2,3,4,5,6: Step 4 PCPC Instruction Memory addr out Registers read1 read2 write w data data1 data2 sign extend add +4 shift add ALUALU Data Memory addr w data r data muxmux muxmux muxmux Fetch 4 Decode 3Execute 2Mem 1

Six instructions 1,2,3,4,5,6: Step 5 PCPC Instruction Memory addr out Registers read1 read2 write w data data1 data2 sign extend add +4 shift add ALUALU Data Memory addr w data r data muxmux muxmux muxmux Fetch 5Decode 4Execute 3 WB 1 (add) Mem 2 (sw)

Six instructions 1,2,3,4,5,6: Step 6 PCPC Instruction Memory addr out Registers read1 read2 write w data data1 data2 sign extend add +4 shift add ALUALU Data Memory addr w data r data muxmux muxmux muxmux Fetch 6 Decode 5 Execute 4Mem 3 (addi) WB 2 (sw: no write)

Six instructions 1,2,3,4,5,6: Step 7 PCPC Instruction Memory addr out Registers read1 read2 write w data data1 data2 sign extend add +4 shift add ALUALU Data Memory addr w data r data muxmux muxmux muxmux Decode 6 Execute 5 Mem 4 (lw) WB 3 (addi)

Six instructions 1,2,3,4,5,6: Step 8 PCPC Instruction Memory addr out Registers read1 read2 write w data data1 data2 sign extend add +4 shift add ALUALU Data Memory addr w data r data muxmux muxmux muxmux Execute 6 Mem 5 (slti) WB 4 (lw)

Six instructions 1,2,3,4,5,6: Step 9 PCPC Instruction Memory addr out Registers read1 read2 write w data data1 data2 sign extend add +4 shift add ALUALU Data Memory addr w data r data muxmux muxmux muxmux Mem 6 (add) WB 5 (slti)

PCPC addr REGISTERS MEMORY R1 R2 WR W Data R Data 1 R Data 2 ALU data ALU CTRL rs rt rd fctnopshamt add rd, rs, rt fetch: load ir, pc=pc+4 decode execute A B w data immedsign extend shift 2 +4 IRIR MRMR z alu out shift 2jump addr

PCPC addr REGISTERS MEMORY R1 R2 WR W Data R Data 1 R Data 2 ALU data ALU CTRL rs rt rd fctnopshamt Multicycle Datapath A B w data immedsign extend shift 2 +4 IRIR MRMR z alu out shift 2jump addr fetch decode execute

PCPC addr REGISTERS MEMORY R1 R2 WR W Data R Data 1 R Data 2 ALU data ALU CTRL rs rt rd fctnopshamt add rd, rs, rt fetch decode:load A,B registers execute A B w data immedsign extend shift 2 +4 IRIR MRMR z alu out shift 2jump addr

PCPC addr REGISTERS MEMORY R1 R2 WR W Data R Data 1 R Data 2 ALU data ALU CTRL rs rt rd fctnopshamt add rd, rs, rt fetch decode execute (2 cycles) load alu out; load register A B w data immedsign extend shift 2 +4 IRIR MRMR z alu out shift 2jump addr

PCPC addr REGISTERS MEMORY R1 R2 WR W Data R Data 1 R Data 2 ALU data ALU CTRL rs rt rd fctnopshamt bne rs, rt, addr fetch: load IR, pc=pc+4 decode execute A B w data immedsign extend shift 2 +4 IRIR MRMR z alu out shift 2jump addr

PCPC addr REGISTERS MEMORY R1 R2 WR W Data R Data 1 R Data 2 ALU data ALU CTRL rs rt rd fctnopshamt bne rs, rt, addr fetch decode: load A B, aluout = immediate (extendx2)+pc execute A B w data immedsign extend shift 2 +4 IRIR MRMR z alu out shift 2jump addr

PCPC addr REGISTERS MEMORY R1 R2 WR W Data R Data 1 R Data 2 ALU data ALU CTRL rs rt rd fctnopshamt bne rs, rt, addr fetch: decode: execute: (1 cycle) compare A, B (holding rs, rt); if neq, load pc with aluout (holding branch addr) A B w data immedsign extend shift 2 +4 IRIR MRMR z alu out shift 2jump addr

PCPC addr REGISTERS MEMORY R1 R2 WR W Data R Data 1 R Data 2 ALU data ALU CTRL rs rt rd fctnopshamt lw rt, offset ( rs) fetch: load IR, pc=pc+4 decode execute A B w data immedsign extend shift 2 +4 IRIR MRMR z alu out shift 2jump addr

PCPC addr REGISTERS MEMORY R1 R2 WR W Data R Data 1 R Data 2 ALU data ALU CTRL rs rt rd fctnopshamt lw rt, offset ( rs) fetch decode: load A B; offset is ready execute A B w data immedsign extend shift 2 +4 IRIR MRMR z alu out shift 2jump addr

PCPC addr REGISTERS MEMORY R1 R2 WR W Data R Data 1 R Data 2 ALU data ALU CTRL rs rt rd fctnopshamt lw rt, offset ( rs) fetch decode execute: (3 cycles): load aluout with addr, load mr with data, load register rt A B w data immedsign extend shift 2 +4 IRIR MRMR z alu out shift 2jump addr

PCPC addr REGISTERS MEMORY R1 R2 WR W Data R Data 1 R Data 2 ALU data ALU CTRL rs rt rd fctnopshamt Multicycle Datapath A B w data immedsign extend shift 2 +4 IRIR MRMR z alu out shift 2jump addr Try these: sw rt, off(rs) j addr andi rd,rs,rt

PCPC addr REGISTERS MEMORY R1 R2 WR W Data R Data 1 R Data 2 ALU data ALU CTRL rs rt rd fctnopshamt Multicycle Datapath A B w data immedsign extend shift 2 +4 IRIR MRMR z alu out

PCPC addr instr INSTR MEM R1 R2 WR W Data R Data 1 R Data 2 ALU DATA MEM ALU CTRL rs rt rd fctn op shamt R-Format: add, slt, sll

PCPC addr instr INSTR MEM R1 R2 WR W Data R Data 1 R Data 2 ALU DATA MEM ALU CTRL rs rt op +4 shift 2 zero BRANCH CTRL muxmux sign extend immed 1632 ADDADD ADDADD I-Format bne

PCPC addr instr INSTR MEM R1 R2 WR W Data R Data 1 R Data 2 ALU DATA MEM ALU CTRL rs rt op zero sign extend immed 1632 I-Format lw, sw addr W Data muxmux R Data

PCPC addr instr INSTR MEM R1 R2 WR W Data R Data 1 R Data 2 ALU DATA MEM ALU CTRL op +4 shift 2 zero BRANCH CTRL muxmux ADDADD ADDADD J-Format address

PCPC addr REGISTERS MEMORY R1 R2 WR W Data R Data 1 R Data 2 ALU data ALU CTRL rs rt rd fctnopshamt Multicycle Datapath A B w data immedsign extend shift 2 +4 IRIR MRMR z alu out shift 2jump addr fetch decode execute