1. ELEN 468 Advanced Logic Design
Lecture 17
MIPS Microprocessor

2. Computer Architecture
CISC
Complex Instruction Set Computer
Intel’s x86, Motorola’s 680x0
RISC
Reduced Instruction Set Computer
MIPS
Microcomputer without Interlocked Pipeline Stages
Millions of Instructions Per Second
Strongly pipelined architecture
DEC’s Alpha, HP’s Precision

3. Registers 32 32-bit (word) registers
$a0 - $a3: argument registers
$v0 - $v1: return values
$ra: return address register
$sp: stack pointer
$fp: frame pointer
$gp: global pointer
$zero: always equals 0
$s0 - $s7: preserved on a procedural call
$t0 - $t9: not preserved by callee on a procedural call
Preservation by callee: values are not changed by
a system/function call.

4. Arithmetic Operations
add a, b, c # a = b + c
add $t0, $s1, $s2
sub a, b, c # a = b – c
sub $s0, $t0, $t1
Arithmetic operations occur only on registers

5. Data Transfer lw $t0, 8($s3) # load $t0 with data from memory
# base address in $s3, offset 8
sw $t0, 48($s3) # store word … …
Byte – 8 bits
Word – 32 bits
Memory in words
Address to byte level 12
101
110 10
1001 8 4
Address
Memory

6. MIPS Fields R-type op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits
I-type op rs rt
address
op: basic operation, also called opcode
rs: the first register source operand
rt:
R-type: the second register source operand
I-type: destination register
rd: the register destination operand
shamt: shift amount in shift instructions
funct: selects the specific variant of the operation in op field, also called function code
address: offset of memory address in data transfer instructions

7. Examples of Machine Codeop rs rt rd
shamt
funct 18 19 17 32
add $s1, $s2, $s3 18 19 17 34
sub $s1, $s2, $s3 op rs rt
address 35 18 17
100
lw $s1, 100($s2) 43 18 17
100
sw $s1, 100($s2)

8. Some Other Instructions
beq $s3, $s4, L1 # go to branch L1, if equal
bne $s3, $s4, L1 # go to branch L1, if not equal
j L1 # jump to branch L1
jr $t0 # jump based on $t0
slt $t0, $s1, $s2 # set value of $t0 to 1, if less than
sll $t2, $s0, 8 # reg $t2 = reg $s0 << 8 bits
srl $t2, $s0, 8 # reg $t2 = reg $s0 >> 8 bits
addi $sp, $sp, 4 # $sp = $sp + 4
nop # do nothing

9. MIPS Addressing Mode Register addressing: the operand is a register
Base or displacement addressing: the operand is at the memory whose address is the sum of a register and a constant
Immediate addressing: the operand is a constant
PC (Program Counter)-relative addressing: address is the sum of PC and a constant in the instruction

10. Steps for MIPS Instructions
Fetch instruction from memory
Read registers while decoding the instruction
Execute the operation or calculate an address
Access an operand in data memory (for lw and sw)
Write the result into a register

11. Implement Instruction Fetch
Add 4
Read address PC
Instruction
Instruction memory

12. Datapath for R-type Instructions5
Read register 1
Control 32
Read data 1 5
Read register 2
Instruction
ALU
Registers 32 5
Write register
Result 32
Read data 2
Write data
Reg_write

13. Example of Instruction Execution Time
Instruction fetch
Register read
ALU operation
Memory access
Register write
Total time lw 2 1 8 sw 7
R-format (add, sub) 6
Branch 5

14. Unpipelined vs. Pipelined2 4 6 8 10 12 14 16 18
lw $t1, 8($s1)
lw $t2, 16($s2)
lw $t3, 12($s3) IF ID
ALU
MEM WB
IF: Instruction fetch
ID: Instruction decode and read register
ALU: Execution or address calculation IF ID
ALU
MEM WB
MEM: Memory access
WB: Write back to reg IF
lw $t1, 8($s1)
lw $t2, 16($s2)
lw $t3, 12($s3) IF ID
ALU
MEM WB IF ID
ALU
MEM WB IF ID
ALU
MEM WB

15. Instruction Sets for Pipelining
All instructions have the same length
There are only a few instruction formats
Memory operands only appear in loads or stores
Operands must be aligned in memory

16. Pipeline Hazards
Situations when the next instruction cannot execute in the following clock cycle
Structural hazards
Control hazards
Data hazards

17. Structural Hazards
Hardware cannot support the combined instructions that we want to execute in the same clock cycle
Example: if there is only one memory, then memory access and instruction fetch cannot be executed simultaneously
Solution: add hardware

18. Control Hazards
Decision-making depends on the result of an instruction that has not been finished
Example: PC following a branch instruction depends if branch is taken or not
Solutions
Predict: execute next instruction anyway, if branch is taken, retract the decision
Dynamic prediction based on smart guess

19. Data Hazards
An instruction cannot be executed until a data is available from another instruction
Example: add $s0, $t1, $t2
sub $t2, $s0, $t3
Solution:
Bypassing: result can be fed to next instruction execution without loading to a register