1. Adapted from Computer Organization and Design, Patterson & Hennessy, UCB ECE232: Hardware Organization and Design Part 9: MIPS Lite 4 th edition: Chapter 4; 3 rd edition: Chapter 5 http://www.ecs.umass.edu/ece/ece232/

2. ECE232: MIPS-Lite 2 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren MIPS-lite processor  Want to build a processor for a subset of MIPS instruction set (“MIPS-lite”) just enough to illustrate key ideas instruction set subset (3 groups): arithmetic-logical: add, sub, and, or, slt memory reference: lw, sw control flow:j, beq can we write real programs with just these?  Need up to 5 steps to execute any instruction in our subset Processor (CPU) Computer Control Datapath IMemory MIPS Instructions DMemory

3. ECE232: MIPS-Lite 3 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Instruction Execution Steps Instruction Fetch Decode, Inc PC and Read Registers ALU Operation, Branch address Data Memory operation Write Back 1. Read IM[PC] 2. Instruction Decode, PC = PC + 4, Register read 3. ALU operation, Branch address computation 4. LW/STORE in Data memory 5. Register Write

4. ECE232: MIPS-Lite 4 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Building a Datapath for MIPS (step 1) PC Instruction Memory Step 1  add $t0,$t0,$t0 add $t0,$s1,$t0 lw $t1,20($s0) sw $t1,4($t0) . PC-4 PC PC+4 PC+8. Flow of execution Step 1: instruction fetch

5. ECE232: MIPS-Lite 5 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Datapath Step 1: Any Instruction PC Instruction Memory (IMem) Address Instruction AddAdd “4” 32-bit adder or ALU wired only for add Clock Once program is loaded, IMem is read-only

6. ECE232: MIPS-Lite 6 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Building a Datapath for MIPS (step 2) PC Registers Step 1 Step 2: Decode and Read Registers add $t0,$s1,$t0 Instruction Memory op rs rt rd shamt funct 0 17 8 8 0 32 R

7. ECE232: MIPS-Lite 7 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Datapath Step 2: Any Instruction Register File Read Register 1 Read data 1 Read data 2 Read Register 2 Write Register Write Data Instruction Control Datapath Control Points 6 op rs rt rd shamt funct R add $t0,$t1,$t2

8. ECE232: MIPS-Lite 8 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Remaining Steps in Executing Instructions  3rd step onwards depends on instruction class  EX: for ALU instructions: add $t0, $t1, $t2 outputs from registers t1 and t2 will be sent to the ALU input  For Memory-reference instruction: lw$t0,20($s0) Address  Base + offset ALUALU

9. ECE232: MIPS-Lite 9 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Building a Datapath for MIPS ( lw step 3) PCRegisters ALUALU Instruction Memory Step 1Step 2Step 3 op rs rt address lw $t0, 20($s0) I

10. ECE232: MIPS-Lite 10 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Datapath Step 3-4: R-format Instructions Registers Read Register 1 Read data 1 ALUALU Read data 2 Read Register 2 Write Register Write Data Instruction Result Zero ALU control 3 32 RegWrite add, sub, and, or [$t1] [$t2] [$t1]  [$t2] { +, -, AND, OR, etc.} [$t3]  [$t1]  [$t2]

11. ECE232: MIPS-Lite 11 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Datapath Step 3: Branch Registers Read Register 1 Read data 1 ALUALU Read data 2 Read Register 2 Write Register Write Data Instruc- tion Zero RegWrite Sign Extend 32 16 AddAdd Branch target To branch control logic PC + 4 from step 1 datapath Mult by 4 beq $t0,$t1,loop ALU control 3 Result [$t0] [$t1]

12. ECE232: MIPS-Lite 12 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Steps 4,5 in Executing lw,sw  4th step depends on instruction class  Ex: for lw: Fetch Data from Memory Data  Mem[Address]  For sw: Put the contents of a register in Memory From Register for SW To register for LW lw $t1,20($s0) sw $t1,4($t0) PCRegisters ALUALU Step 1 Step 2 Step 3 Data Memory Step 4 Instruction Memory  5th step only for lw; rest are done  for lw: Write Result Reg[rt]  Data

13. ECE232: MIPS-Lite 13 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Datapath Step 3-5: Load/Store Registers Read Register 1 Read data 1 ALUALU Read data 2 Read Register 2 Write Register Write Data Instruc- tion Zero ALU control RegWrite Address Read data Write Data Sign Extend 32 16 DMem MemRead MemWrite lw $t0,24($s3) op rs rt address Result [$s3] “24” [$s3]+24

14. ECE232: MIPS-Lite 14 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Compose Datapath: R-form + Load/Store Registers Read Register 1 Read data 1 ALUALU Read data 2 Read Register 2 Write Register Write Data Instruction Zero ALU control 3 RegWrite Address Read data Write Data Sign Extend 32 16 DMem MemRead MemWrite 1Mux01Mux0 MemTo- Reg 0=R-form 1=L/S MuxMux ALUSrc 0 = R-format 1 = Load/Store Add muxes

15. ECE232: MIPS-Lite 15 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Compose Datapath: + IMem + PC Registers Read Reg1 Read data1 ALUALU Read data2 Read Reg2 Write Reg Write Data Zero ALU control 4 RegWrite Address Read data Write Data Sign Extend 32 16 DMem MemRead MemWrite MuxMux MemTo- Reg MuxMux ALUSrc Read Addr Instruc- tion IMem “4” PCPC addadd

16. ECE232: MIPS-Lite 16 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Compose Datapath: + Branch Registers Read Reg1 Read data1 ALUALU Read data2 Read Reg2 Write Reg Write Data Zero ALUcon RegWrite Address Read data Write Data Sign Extend 32 16 DMem MemRead MemWrite MuxMux MemTo- Reg MuxMux ALUSrc Read Addr Instruc- tion IMem “4” PCPC addadd addadd << 2 MuxMux PCSrc “Left Shift 2” module Supports all MIPS-lite instructions? (slt and ?)

17. ECE232: MIPS-Lite 17 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Datapath: Register fields  Destination registers may differ across instruction formats: R-format: [rd]  [rs] op [rt] add $t0,$s0,$s1 For this instruction, bits 11-15 are the destination (t0), which should be connected to the write reg. inputs I-format:[rt]  mem [ [rs] + imm16 ] lw $t0,24($s3) For this instruction, bits 16-20 should go to the write reg. port. Bits 0-15 go to the ALU as address Connection to the write reg. port changes!  Solution? mux to the rescue! oprsrtrdfunctshamt 6 bits5 bits 6 bits oprsrtoffset 6 bits5 bits 16 bits

18. ECE232: MIPS-Lite 18 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Datapath (add RegDst Mux) Regs Read Reg1 Read data1 ALUALU Read data2 Read Reg2 Write Reg Write Data Zero ALU- con RegWrite Address Read data Write Data Sign Extend DMem MemRead MemWrite MuxMux MemTo- Reg MuxMux Read Addr Instruc- tion IMem 4 PCPC addadd addadd << 2 MuxMux PCSrc ALU- src MuxMux 25:21 20:16 15:11 RegDst 15:0 31:0

19. ECE232: MIPS-Lite 19 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Datapath: Determine next PC  What if instruction is a conditional branch ( beq )? if operands equal, take branch (PC gets PC+4+offset) else PC gets PC+4  Therefore, set control point PCSrc = 1 if and only if beq and Zero asserted

20. ECE232: MIPS-Lite 20 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Datapath (add Branch control point) Regs Read Reg1 Read data1 ALUALU Read data2 Read Reg2 Write Reg Write Data Zero ALU- con RegWrite Address Read data Write Data Sign Extend DMem MemRead MemWrite MuxMux MemTo- Reg MuxMux Read Addr Instruc- tion IMem 4 PCPC addadd addadd << 2 MuxMux ALU- src MuxMux 25:21 20:16 15:11 RegDst 15:0 31:0 Branch PCSrc

21. ECE232: MIPS-Lite 21 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Adding Control  CPU = Datapath + Control  Single-Cycle Design: Instruction takes exactly one clock cycle Datapath units used only once per cycle Writable state updated at end of cycle  What must be “controlled”? Multiplexors (Muxes) Writable components: Register File, Data Memory (DMem) what about PC? IMem? ALU (which operation?)

22. ECE232: MIPS-Lite 22 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Processor = Datapath + Control Control Logic op rs rt rd shamt funct R-format instruction To datapath 6 6  Single-Cycle Design: everything happens in one clock cycle until next falling edge of clock, processor is just one big combinational circuit!!!  Control is a combinational circuit where the output is a function of the inputs outputs? control points in datapath inputs? the current instruction! (opcode, funct control everything)

23. ECE232: MIPS-Lite 23 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Defining Control  Note that funct field only present in R-format instruction - funct controls ALU only  To simplify control, define Main control, ALU control separately – using multiple levels will also increase speed – important optimization technique  ALUop inputs will be defined Control Logic Main Control ALU control op funct op funct ALU- con ALUop

24. ECE232: MIPS-Lite 24 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Defining ALU Control ALUcon ALUALU Zero Result ALUcon ALU functionInstruction(s) supported 0000ANDR-format (and) 0001ORR-format (or) 0010addR-format (add), lw, sw 0110subtractR-format (sub), beq 0111 set on less thanR-format (slt) 1100 NOR R-format (nor) ABAB

25. ECE232: MIPS-Lite 25 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Defining ALU Control InstructionDesired opcodeALU ActionALUOpfunctALUcon lwadd 00xxxxxx 0010 swadd 00xxxxxx 0010 beqsubtract 01xxxxxx 0110 R-typeadd 10100000 (add) 0010 R-typesubtract 10100010 (sub) 0110 R-typelogical AND 10100100 (and) 0000 R-typelogical OR 10100101 (or) 0001 R-typeset on less 10101010 (slt) 0111 ALUOp Funct Field a1a0f5f4f3f2f1f0ALUcon 00xxxxxx 0010 x1xxxxxx 0110 1xxx0000 0010 1xxx0010 0110 1xxx0100 0000 1xxx0101 0001 1xxx1010 0111 Don’t Cares c3 c2 c1 c0

26. ECE232: MIPS-Lite 26 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren OpCode field 000001010011100101110111 000R-formatjjalbeqbneblezbgtz 001addiaddiusltisltiuandiorixori 010 011llolhitrap 100lblhlwlbulhu 101sbshsw 110 111

27. ECE232: MIPS-Lite 27 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Function field 000001010011100101110111 000sllsrlsrasllvsrlvsrav 001jrjalr 010mfhimthimflomtlo 011multmultudivdivu 100addaddusubsubuandorxornor 101sltsltu 110 111

28. ECE232: MIPS-Lite 28 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Fully Minimized ALU Control F3 F2 F1 F0 ALUOp ALUcon 4th bit=0 funct c2 c1 c0 a0 a1  From the truth table, output signals can be easily derived because of don’t cares  c2 = a0 OR (a1 AND f1)  c1 = (Not a1) OR (Not f2)  c0 (lsb) = a1 AND (f3 OR f0)  ALUOp is supplied by the main control unit (to be designed) a1,0 f5,4,3,2,1,0 ALUcon 0 0 x x x x x x 0010 X 1 x x x x x x 0110 1 x x x 0 0 0 0 0010 1 x x x 0 0 1 0 0110 1 x x x 0 1 0 0 0000 1 x x x 0 1 0 1 0001 1 x x x 1 0 1 0 0111

29. ECE232: MIPS-Lite 29 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Datapath + ALU Control Registers Read Reg1 Read data1 ALUALU Read data2 Read Reg2 Write Reg Write Data Zero ALU- con RegWrite Address Read data Write Data Sign Extend DMem MemRead MemWrite MuxMux MemTo- Reg MuxMux Read Addr Instruc- tion IMem “4” PCPC addadd addadd << 2 MuxMux PCSrc ALU Control Instr[5:0] ALUOp ALU- src

30. ECE232: MIPS-Lite 30 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Datapath With Control

31. ECE232: MIPS-Lite 31 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Adding Jumps  Update PC with concatenation of Top 4 bits of old PC 26-bit jump address 00  Need an extra control signal decoded from opcode 2address 31:2625:0 Jump

32. ECE232: MIPS-Lite 32 Adapted from Computer Organization and Design, Patterson&Hennessy, UCB, Kundu,UMassKoren Datapath With Jumps Added