1. Sample Code (Simple) Run the following code on a pipelined datapath: add1 2 3 ; reg 3 = reg 1 + reg 2 nand 4 5 6 ; reg 6 = reg 4 & reg 5 lw2 4 20 ; reg 4 = Mem[reg2+20] add2 5 5 ; reg 5 = reg 2 + reg 5 sw 3 7 10 ; Mem[reg3+10] =reg 7

2. PC Inst mem Register file MUXMUX ALUALU MUXMUX 1 Data memory ++ MUXMUX IF/ ID ID/ EX EX/ Mem Mem/ WB MUXMUX Bits 0-2 Bits 16-18 op dest offset valB valA PC+1 target ALU result op dest valB op dest ALU result mdata eq? instruction 0 R2 R3 R4 R5 R1 R6 R0 R7 regA regB Bits 22-24 data dest

3. PC Inst mem Register file MUXMUX ALUALU MUXMUX 1 Data memory ++ MUXMUX IF/ ID ID/ EX EX/ Mem Mem/ WB MUXMUX Bits 0-2 Bits 16-18 noop 0 0 0 0 00 0 0 0 0 0 0 0 0 9 12 18 7 36 41 0 22 R2 R3 R4 R5 R1 R6 R0 R7 Bits 22-24 data dest Initial State

4. PC Inst mem Register file MUXMUX ALUALU MUXMUX 1 Data memory ++ MUXMUX IF/ ID ID/ EX EX/ Mem Mem/ WB MUXMUX Bits 0-2 Bits 16-18 noop 0 0 0 0 01 0 0 0 0 0 0 0 0 add 1 2 3 9 12 18 7 36 41 0 22 R2 R3 R4 R5 R1 R6 R0 R7 Bits 22-24 data dest Fetch: add 1 2 3 Time: 1

5. PC Inst mem Register file MUXMUX ALUALU MUXMUX 1 Data memory ++ MUXMUX IF/ ID ID/ EX EX/ Mem Mem/ WB MUXMUX Bits 0-2 Bits 16-18 add 3 3 9 36 12 0 0 noop 0 0 0 0 0 0 nand 4 5 6 9 12 18 7 36 41 0 22 R2 R3 R4 R5 R1 R6 R0 R7 1 2 Bits 22-24 data dest Fetch: nand 4 5 6 nand 4 5 6 add 1 2 3 Time: 2

6. PC Inst mem Register file MUXMUX ALUALU MUXMUX 1 Data memory ++ MUXMUX IF/ ID ID/ EX EX/ Mem Mem/ WB MUXMUX Bits 0-2 Bits 16-18 nand 6 6 7 18 23 4 45 add 3 9 noop 0 0 0 0 lw 2 4 20 9 12 18 7 36 41 0 22 R2 R3 R4 R5 R1 R6 R0 R7 4 5 Bits 22-24 data dest Fetch: lw 2 4 20 lw 2 4 20 nand 4 5 6 add 1 2 3 Time: 3 36 9 1 3 3

7. PC Inst mem Register file MUXMUX ALUALU MUXMUX 1 Data memory ++ MUXMUX IF/ ID ID/ EX EX/ Mem Mem/ WB MUXMUX Bits 0-2 Bits 16-18 lw 4 20 18 9 34 8 -3 nand 6 7 add 3 45 0 0 add 2 5 8 9 12 18 7 36 41 0 22 R2 R3 R4 R5 R1 R6 R0 R7 2 4 Bits 22-24 data dest Fetch: add 2 5 5 add 2 5 5 lw 2 4 20 nand 4 5 6 add 1 2 3 Time: 4 18 7 2 6 6 45 3

8. PC Inst mem Register file MUXMUX ALUALU MUXMUX 1 Data memory ++ MUXMUX IF/ ID ID/ EX EX/ Mem Mem/ WB MUXMUX Bits 0-2 Bits 16-18 add 5 5 7 9 45 23 29 lw 4 18 nand 6 -3 0 0 sw 3 7 10 9 45 18 7 36 41 0 22 R2 R3 R4 R5 R1 R6 R0 R7 2 5 Bits 22-24 data dest Fetch: sw 3 7 10 sw 3 7 10 add 2 5 5 lw 2 4 20 nand 4 5 6 add Time: 5 9 20 3 4 -3 6 45 3

9. PC Inst mem Register file MUXMUX ALUALU MUXMUX 1 Data memory ++ MUXMUX IF/ ID ID/ EX EX/ Mem Mem/ WB MUXMUX Bits 0-2 Bits 16-18 sw 7 10 22 45 5 9 16 add 5 7 lw 4 29 99 0 9 45 18 7 36 -3 0 22 R2 R3 R4 R5 R1 R6 R0 R7 3 7 Bits 22-24 data dest No more instructions sw 3 7 10 add 2 5 5 lw 2 4 20 nand Time: 6 9 7 4 5 5 29 4 -3 6

10. PC Inst mem Register file MUXMUX ALUALU MUXMUX 1 Data memory ++ MUXMUX IF/ ID ID/ EX EX/ Mem Mem/ WB MUXMUX Bits 0-2 Bits 16-18 15 55 sw 7 22 add 5 16 0 0 9 45 99 7 36 -3 0 22 R2 R3 R4 R5 R1 R6 R0 R7 Bits 22-24 data dest No more instructions sw 3 7 10 add 2 5 5 lw Time: 7 45 5 10 7 16 5 99 4

11. PC Inst mem Register file MUXMUX ALUALU MUXMUX 1 Data memory ++ MUXMUX IF/ ID ID/ EX EX/ Mem Mem/ WB MUXMUX Bits 0-2 Bits 16-18 sw 7 55 0 9 45 99 16 36 -3 0 22 R2 R3 R4 R5 R1 R6 R0 R7 Bits 22-24 data dest No more instructions sw 3 7 10 add Time: 8 22 55 22 16 5

12. PC Inst mem Register file MUXMUX ALUALU MUXMUX 1 Data memory ++ MUXMUX IF/ ID ID/ EX EX/ Mem Mem/ WB MUXMUX Bits 0-2 Bits 16-18 9 45 99 16 36 -3 0 22 R2 R3 R4 R5 R1 R6 R0 R7 Bits 22-24 data dest No more instructions sw Time: 9

13. Time graphs Time: 1 2 3 4 5 6 7 8 9 add nand lw add sw fetch decode execute memory writeback