Ultrafast 16-channel ADC for NICA-MPD Forward Detectors A.V. Shchipunov Join Institute for Nuclear Research Dubna, Russia

Motivation  Create a PCB Design for digitizing signals from NICA-MPD’s Forward Detectors

Time Projection Chamber Outer radius~ 110 cm Inner radius27 cm Drift length~ 150 cm Number of sectors (each side)12 Total number of readout chambers24 (12 - each side) Drift time~ ms Multiplicity for charged particles~ 500 Total pad/channels number~ dE/dx resolution~ 6% Spatial resolution (s x, s y, s z )0.6 x 1.0 x 2.0 mm Maximal rate~ 6 kHz Two track resolution~ 1 cm

Time Of Flight Radius from the beam line1.3 m Time resolution100 ps Max momentum of π/K system separated better than 2,5 σ1,3 GeV/c

 16 input channels  high sampling rate — up to 5 GHz — for each channel  VME compatible PCB design  Self-calibration  Contain 72-bit QDR SRAM  Spartan-6 FPGA family

Specifications and readout characteristics Specifications Number of channels16 Effective resolution11.5 bits Bandwidth -3dB950 MHz Full scale range±1V on 50 Ω Sampling speed1, 1.7, 2, 3.4, 4, 5 GS/s Sampling ring buffer1024 samples FPGA buffer size4Mb / 256k samples SRAM buffer size64Mb / 4M samples Readout characteristics Waveform size DRS readout time7,8 μs31 μs Event rate to RAM124 kHz31 kHz FPGA buffer1024 waveforms256 waveforms SRAM buffer16384 waveforms4096 waveforms

Functional diagram 16 Input Channels Preamplifiers Trigger logic Sampling signals ADCs FPGA SRAM buffer VME itnerface Self-calibration Trigger

DRS4 — Functional block diagram  Sampling speed – 0,7 to 5 GSPS  8+1 channels with 1024 storage cells each  Differential inputs with 950 MHz bandwidth  Readout time: 30ns * number of samples  Simultaneous reading and writing

CY7C1515KV18 — 72-Mb QDR® II SRAM 4-Word Burst Architecture  Separate independent read and write data ports  4-word burst for reducing address bus frequency  DDR interfaces for on both read and write ports  Full data coherency, providing most current data

FPGA Spartan 6 — XC6SLX150T  logic cells  configurable logic blocks: slices, flip-flops, 1,355 MAX distributed RAM  RAM Blocks  4 memory controller blocks  6 banks  540 user I/O pins

AD9788 — 16-bit 800 MSPS DAC  Adjustable analog output: 8.7mA to 31.7mA, RL = 25Ω to 50Ω  Internal digital upconversion capability  High performance, low noise PLL clock multiplier  Digital inverse sinc filter

ADC16V-DRS 16 input channels SRAM buffer 2 x DRS4 & 2 x ADCs Preamplifiers & analog switches FPGA TxDAC VME interface TTC ConnectorOutput connectors

ADC8BE-DRS FPGA EtherNET interface 8 input channels Preamplifiers & analog switches DRS4 & ADC TxDAC