IO Controller Module Arbitrates IO from the CCP Physically separable from CCP –Can be used as independent data logger or used in future projects. Implemented.
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Presentation on theme: "IO Controller Module Arbitrates IO from the CCP Physically separable from CCP –Can be used as independent data logger or used in future projects. Implemented."— Presentation transcript:
IO Controller Module Arbitrates IO from the CCP Physically separable from CCP –Can be used as independent data logger or used in future projects. Implemented using a Xilinx Spartan 3E FPGA (XCS500E-PQ208)
FPGA Selection FPGA chosen for highest gate & largest pin count BGA is not desirable due to board routing complexity Package DeviceVQ100CP132TQ144PQ208FT256FG320FG400FG484 XC3S100E XXX XC3S250E XXXXX XC3S500E XX XXX XC3S1200E XXX XC3S1600E XXX
Programming Interface USB UART converter does most of the work for us PM FLASH is programmed from UART Second UART is provided for CCP configuration
FLASH & SD Card SST’s 4MB FLASH stores application program Shares SPI Bus with SD Card for data logging and removable storage
CCP Interface High speed serial interface to CCP along with interrupt requests Pins on FPGA and header are reserved specifically for implementing GPMC in the future
FPGA Configuration On power-up, FPGA is automatically configured by the XCF02S which stores rigidware. Rigidware can be changed via JTAG interface
Analog to Digital Converter Simultaneous samples of 8 channels Supports differential inputs Adjustable sampling range –Range is digitally controlled by adjacent DAC
Digital IO PWM signals connected directly to IOB (3.3v levels) Configurable IO Ports have adjustable logic levels. –User supplies voltage reference –TXB0108 detects direction of communication without the need for direction control
Logic Cost Analysis LUTs Plasma Core3306 CCP Interface300 PWM IO Controller300 Analog Controller230 Configurable IO Port710 Number of IO Ports:5 Total LUTs Used:7686 Available LUTs9312 Remaining LUTs1626 Design with 5 IO ports uses approximately 80% of available logic –20% for uncertainty in estimates and potential overhead for PAR of large designs.
Throughput Estimation Dummy DAQ program written for MAV set of peripherals –Single sample can be executed in ~420 clock cycles @ 25 MHz –Assuming SPI communication to IMU is done without interrupts, CPU must stall for duration of transfer (~200 cycles @ 2 MHz) –Results in theoretical sample rate of 30 kHz