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Preliminary Design of Calorimeter Electronics Shudi Gu June 2002.

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Presentation on theme: "Preliminary Design of Calorimeter Electronics Shudi Gu June 2002."— Presentation transcript:

1 Preliminary Design of Calorimeter Electronics Shudi Gu June 2002

2 CsI Crystal 9864 CsI crystals 2 PIN photo diodes each crystal 0.8fc/MeV sensitivity CsI crystal resolution:

3 Operation Conditions & Specifications System clock20MHz L1 trigger latency 3.2  s Single channel event rate≤1KHz Range of charge0.5fc~1500fc Resolution of charge (Energy)0.16fc (200KeV) Number of channel9864 Integral nonlinearity1% (before correction) Cross talk0.3% Dynamic range15Bit Information to triggerAnalogue “sum” of 8 channels Gain adjustable on line≤ 20% nonuniformity

4 Block Diagram From Detector Post amplifier Q Module Test Controller Fan-out Trigger TEST, DAC CLK L1 VMEVME L1 reset Buffer full CLK L1 L1 reset Buffer full L1 L1 reset Buffer full SCLK, DIN Analog Sum Preamplifier

5 Low noise charge sensitive amplifier 1 AMP/diode, 2 AMPs/crystal Average of 2 AMP outputs to improve S/N Average of 2 AMPs or one of the 2 AMPs can be selected by jumpers on Post AMP when one AMP fails Calibration circuit at the input 20 wire twisted cable/Ch to Post AMP

6 Preamplifier Specification Gain1mV/fc ENC 0.16fc (80pf input capacitance) Dynamic Range0.5fc ~ 1500fc Output decay time 50  s Max linear output2V

7 Post Amplifier ½(A+B), A, B can be selected CR-(RC) 2 with pole-zero cancellation shaping,  =1  s Gain adjustable with digital potentiometer Analogue sum for trigger Differential connection with Pre-AMP and Q module A+B A B CR (RC) 2 From Test Controller To Q Module To Trigger ∑ A B From Preamplifier

8 Q Module 3 FADCs sample signals from 3 different gain AMPs Delay samples with pipeline to wait for 3.2  s trigger latency L1 Find peak during 2.5  s after L1 arrival Select peak, make range encoding & compression, store data in buffer Inner trigger for radiation source calibration & adjusting gain 9U VME module, 32ch/module ×.25 Pipeline ×1 ×8 Pipeline Peak Selec. Range Encoding Compress Peak Buffer From Post AMP. FADC Disc. Delay L1 Out. Trig Inn. Trig Thr. Register

9 Three Range Digitization Three 10Bit FADCs with 3 ranges to get 15Bit dynamic range from 0.08MeV to 2.5GeV Small resolution degradation due to digitization RangeGainFull ScaleMin. EnergyDigital Res.CsI Res.Res. Increa. High×0.252.5Gev0.625Gev1.4×10 -3 2.1×10 -2 0.2% Middle×10.625Gev0.078Gev2.3×10 -3 2.9×10 -2 0.3% Low ×8 0.078Gev 20Mev 1.1×10 -3 3.7×10 -2 0.04% 0.6Mev3.5×10 -2 7.3×10 -2 11%

10 System Dynamic Range Dynamic range of digitization is wider than the charge measurement range Charge measurement precision is not infected by noise and digital resolution seriously Noise σ Q = 0.16fc 200KeV 2.5GeV 2000fc 75KeV 0.06fc Dynamic range of digitization (15Bits) Charge measurement range 1500fc 1.875GeV 0.5fc 625KeV

11 Test Controller Fan out and send 20MHz clock, L1 and L1 reset from trigger system to Q modules in the same crate for collision mode Generate 20MHz clock, L1, DAC and Test pulse for calibration mode Generate 20MHz clock for inner trigger mode. Test system with radiation source Generate 20MHz clock, serial clock and data for gain adjustment mode 1 Trigger Delay Shaping 2 3 1 2 3 1 2 3 + 5V Trigger 16bit DAC DIN SCLK DAC Test L1 CLK Address 20MHz Crystal Frequency Divider PLD VMEVME 1.Inner trigger 2.Calibration & gain adj. 3.Outer trigger

12 Local Buffer Readout Separate VME addresses and buffers for trigger number, Hit Map and data of 32 channels Only read channels pointed by Hit Map OR Read all channels without compression with Linked List DMA Enough readout speed with Linked List DMA A Q module for testing is designing with local buffer

13 Global Buffer Readout Controller on board moves compressed data from local buffers to a global buffer Read data from the global buffer with Direct DMA Higher speed but more difficult to design & debug than local buffer Final Q module will be designed with global buffer

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