1. Iwaki System Readout Board User’s Guide
Last update /6

3. What you need (10cm2 m-PIC)
DC power supply
+3.3V : 1.8A, +2.5V : 1.2A, -2.5V : 1.2A
VME memory board & cable ×2
Network card (for SiTCP) & hub (Do Not connect external network)
Some logic modules (NIM or FPGA)

4. First… You need to make Power Supply Cable and trigger cable.
-2.5V AGND +2.5V AGND +3.3V DGND

5. Layout & Circuit CR2 Encoder
Encoder

6. Trigger I/O All signals are LVDS Input Output
DAQ Reset (FIFOs and buffers clear)
Count Reset (Reset Event No.)
Clock Reset (Reset absolute clock)
Trigger
Transfer
Clear
FPGA Reset (Re-download FPGA logic)
Output
Data Exist
Hit (TPC Hit)
Transfer end
Process
FIFO Full

7. DAQ Internal Logic Clock RST CLK FPGA Hit Data exist Transfer or Clear
Analog 4ch
ADC 65MHz
10bit
Clock RST
CLK
FPGA
Ring Buf.
FIFO
Data
format
　　To Memory Board
FIFO
　Digital 128ch
CMOS 2.5
Ring Buf.
FIFO
Data format
FIFO
Hit
Data exist
Transfer or Clear
Trigger
Process
Tr. end

8. Timing Chart (Not fixed)
Pulses are determined by level.

9. Other components Potentiomater R9 Tuning FADC offset.
Dip switch (Not Fixed)
0 : FADC & TPC read speed ON : 50MHz, OFF : 60MHz(FADC), 100MHz(TPC)
1 : Memory board writing speed ON : 25MHz, OFF : 50MHz
2 : SiTCP Reset
3 : Anode or Cathode (SiTCP IP address ) ON : Anode(IP:100), OFF : Cathode(IP:101)

10. Data Event data Header (4) FADC Data (2048) Encoder Data (～1500)
Footer (1)(ALL H : 0xffffffff)

11. Header (Not Fixed) Bit [31:30] (2bit) [29:28] (2bit) [27:0] (28bit)
Flag1
Flag2
Event information 00
Event No. 01
Depth 10
Num. of TPC Hit 11
Absolute time (100MHz)

12. FADC Data Bit [31:30] (2bit) [29:20] (10bit) [19:10] (10bit)
Flag1
ADC1
ADC2
Clock(0～1023) 備考 10
ch0
ch1
Clock(60MHz) 11
ch2
ch3

13. All 0/1 signals from 1 chip (16strips)
Hit Data
Bit
[31:30] (2bit)
[29:26] (4bit)
[25:10] (16bit)
[9:0] (10bit)
Flag
Chip No
Hit
Clock(0～1023) 備考 01
No. of ASIC chips 0～7
All 0/1 signals from 1 chip (16strips)
Clock(100MHz)
Output data only when 128 hit signals are not all 0.

14. DAC Set Vth level of whole Board. DAC level for each ch.
Set using SiTCP.
Still in writing…