Fast Waveform Digitizing in Radiation Detection using Switched Capacitor Arrays Stefan Ritt Paul Scherrer Institute, Switzerland
Sept 25th, 2009CMOS ET Vancouver2 Question ? 4 channels 5 GSPS 1 GHz BW 8 bit (6-7) 15k$ 4 channels 5 GSPS 1 GHz BW 8 bit (6-7) 15k$ 4 channels 5 GSPS 1 GHz BW 11.5 bits 1k$ USB Power 4 channels 5 GSPS 1 GHz BW 11.5 bits 1k$ USB Power
Sept 25th, 2009CMOS ET Vancouver3 The need for speed Det chan Q-ADC Disc. TDC Trigger Traditional technique Gated charge ADCs Constant Fraction Disc. Time-to-Digital Conv. High rate applications Pile-up becomes an issue Waveform digitizing Issues: Limited speed and resolution High channel counts Power consumption FADC Costs Det chan FADC Moving average baseline hits Needed: >3 GSPS 12 bit
Sept 25th, 2009CMOS ET Vancouver4 Switched Capacitor Array Shift Register Clock IN Out “Time stretcher” GHz MHz Waveform stored Inverter “Domino” ring chain 0.2-2 ns FADC 33 MHz
Sept 25th, 2009CMOS ET Vancouver5 DRS4 Designed for the MEG experiment at PSI, Switzerland UMC 0.25 m 1P5M MMC process (UMC), 5 x 5 mm 2, radiation hard 8+1 ch. each 1024 cells Differential inputs, differential outputs Sampling speed 700 MHz … 5 GHz, PLL stabilized Readout speed 30 MHz, multiplexed or in parallel
Sept 25th, 2009CMOS ET Vancouver6 Comparison with other chips MATACQ D. Breton LABRADOR G. Varner DRS4 this talk Bandwidth (-3db) 300 MHz> 1000 MHz950 MHz Sampling frequency 50 MHz…2 GHz10 MHz … 3.5 GHz700 MHz … 6 GHz Full scale range ±0.5 V+0.4 …2.1 V±0.5 V Effective #bits 12 bit10 bit11.5 bit Sample points 1 x 25209 x 2569 x 1024 Frequency PLL YESNOYES Digitization 5 MHzN/A30 MHz Readout dead time 650 s150 s3 s – 370 s Integral nonlinearity ± 0.1 % ± 0.05% Radiation hard No Yes (chip) Board V1729 (CAEN)-V17xx (CAEN)
Sept 25th, 2009CMOS ET Vancouver7 Switched Capacitor Array Pros (DRS4 chip) High speed (5 GHz) high resolution (11.5 bit resol.) High channel density (9 channels on 5x5 mm 2 ) Low power (10-40 mW / channel) Low cost (~ 10$ / channel) Cons No continuous acquisition Limited sampling depth Nonlinear timing tt tt tt tt tt Goal: Minimize Limitations
Sept 25th, 2009CMOS ET Vancouver8 How to minimize dead time ? Fast analog readout: 30 ns / sample Parallel readout Region-of-interest readout Simultaneous write / read AD9222 12 bit 8 channels
Sept 25th, 2009CMOS ET Vancouver9 ROI readout mode readout shift register Trigger stop normal trigger stop after latency Delay delayed trigger stop Patent pending! 33 MHz e.g. 100 samples @ 33 MHz 3 us dead time 300,000 events / sec. e.g. 100 samples @ 33 MHz 3 us dead time 300,000 events / sec.
Sept 25th, 2009CMOS ET Vancouver12 Interleaved sampling delays (167ps/8 = 21ps) G. Varner et al., Nucl.Instrum.Meth. A583, 447 (2007) 6 GSPS * 8 = 48 GSPS Possible with DRS4 if delay is implemented on PCB
Sept 25th, 2009CMOS ET Vancouver13 Trigger and DAQ on same board Using a multiplexer in DRS4, input signals can simultaneously digitized at 65 MHz and sampled in the DRS FPGA can make local trigger (or global one) and stop DRS upon a trigger DRS readout (5 GHz samples) though same 8-channel FADCs analog front end DRS FADC 12 bit 65 MHz MUX FPGA trigger LVDS SRAM DRS4 global trigger bus “Free” local trigger capability without additional hardware
Sept 25th, 2009CMOS ET Vancouver15 Bandwidth Passive Input: Bandwidth is determined by bond wire and internal bus resistance/capacitance: 850 MHz (QFP), 950 MHz (QFN), ??? (flip-chip) Active Inputs: ~300 MHz with current CMOS technology (MATACQ) Near future: 130 nm technology might improve this slightly 850 MHz (-3dB) QFP package Measurement
Sept 25th, 2009CMOS ET Vancouver16 Timing jitter t1t1 t2t2 t3t3 t4t4 t5t5 Inverter chain has transistor variations t i between samples differ “Fixed pattern aperture jitter” “Differential temporal nonlinearity” TD i = t i – t nominal “Integral temporal nonlinearity” TI i = t i – i t nominal “Random aperture jitter” = variation of t i between measurements Inverter chain has transistor variations t i between samples differ “Fixed pattern aperture jitter” “Differential temporal nonlinearity” TD i = t i – t nominal “Integral temporal nonlinearity” TI i = t i – i t nominal “Random aperture jitter” = variation of t i between measurements TD 1 TI 5
Sept 25th, 2009CMOS ET Vancouver17 Fixed jitter calibration Fixed jitter is constant over time, can be measured and corrected for Several methods are commonly used Most use sine wave with random phase and correct for TD i on a statistical basis Fixed jitter is constant over time, can be measured and corrected for Several methods are commonly used Most use sine wave with random phase and correct for TD i on a statistical basis
Sept 25th, 2009CMOS ET Vancouver18 Fixed Pattern Jitter Results TD i typically ~50 ps RMS @ 5 GHz TI i goes up to ~600 ps Jitter is mostly constant over time, measured and corrected Residual random jitter (RMS) 25 ps MATACQ 10 ps Labrador 3-4 ps DRS4 SCA technology can replace high resolution TDCs
Applications of SCA Chips What can we do with this technology?
Sept 25th, 2009CMOS ET Vancouver20 On-line waveform display click template fit pedestal histo 848 PMTs “virtual oscilloscope”
Sept 25th, 2009CMOS ET Vancouver21 Pulse shape discrimination Leading edge Decay time AC-coupling Reflections Example: / source in liquid xenon detector (or: /p in air shower)
Sept 25th, 2009CMOS ET Vancouver22 -distribution = 21 ns = 34 ns Waveforms can be clearly distinguished = 21 ns = 34 ns Waveforms can be clearly distinguished
Sept 25th, 2009CMOS ET Vancouver23 Template Fit Determine “standard” PMT pulse by averaging over many events “Template” Find hit in waveform Shift (“TDC”) and scale (“ADC”) template to hit Minimize 2 Compare fit with waveform Repeat if above threshold Store ADC & TDC values Experiment 500 MHz sampling Pile-up can be detected if two hits are separated in time by ~rise time of signal
Sept 25th, 2009CMOS ET Vancouver24 Experiments using DRS chip MAGIC-II 400 channels DRS2 MEG 3000 channels DRS4 BPM for XFEL@PSI 1000 channels DRS4 (planned) MACE (India) 400 channels DRS4 (planned) PET
Sept 25th, 2009CMOS ET Vancouver25 Datasheet http://drs.web.psi.ch/datasheets
Sept 25th, 2009CMOS ET Vancouver26 Evaluation Board DRS4 can be obtained from PSI on a “non-profit” basis Delivery “as-is” Costs ~ 15-20 CAN$/chn USB Evaluation board as reference design Anybody wants to build a pocket scope?
Sept 25th, 2009CMOS ET Vancouver27 Conclusions This is Exciting Stuff! DRS4 has 6 GHz, 1024 sampling cells per channel, 9 channels per chip, 11.5 bit vertical resolution, 4 ps timing accuracy, other chips similar More development in the pipeline Fast waveform digitizing with SCA chips will have a big impact on particle detection in the next future Other fields should benefit from this development LABRADOR: http://www.phys.hawaii.edu/~idlab/ MATACQ: http://matacq.free.fr/ DRS4: http://drs.web.psi.ch