1. P. Baron CEA IRFU/SEDI/LDEFACTAR Meeting Santiago de Compostela March 11, 2008 1 A review of AFTER+ chip Its expected requirements At this time, AFTER+ must fit the specifications of: ACTAR/GANIL TPC/GLAD/R3B/FAIR TPC&ACTIVE TARGET/MSU TPC/CENBG

2. ACTAR Meeting Santiago de Compostela March 11, 2008 2 AFTER+: Architecture Main features for AFTER+: 72 Analog Channels; Slow Control & test.72 Analog Channels; Slow Control & test. Main features for the channel Input Current Polarity: positive or negative.Input Current Polarity: positive or negative. CSA + PZC + Filter (semi-Gaussian order 2).CSA + PZC + Filter (semi-Gaussian order 2). [Possibility to bypass the CSA and to enter directly to the filter or SCA input]. 511 analog memory cells.511 analog memory cells. Auto Triggering: discriminator + threshold (DAC) + inhibition.Auto Triggering: discriminator + threshold (DAC) + inhibition. Main features for the readout Analog OR of the 72 discriminator outputs [1 current output].Analog OR of the 72 discriminator outputs [1 current output]. Address of the hit channel (through slow control link).Address of the hit channel (through slow control link). 4 SCA readout modes.4 SCA readout modes. Serial Interface Mode CK In Test CSA;CR;SCAin (N°1) Asic “Spy” Mode Readout Mode AFTER+ 511 cells SCAFILTER tpeak CSA 1 channel x72in(76out) 76 to 1 SCA MANAGER SLOW CONTROL W / R CK ADC TEST Charge range Power on Reset BUFFER Σ 72 discriminator outputs ADC DAC Discri inhibit external 12-bit ADC [AD9229] BUFFER

3. ACTAR Meeting Santiago de Compostela March 11, 2008 3 ADC AFTER+ SCA FILTER CSA 1 channel x72in(76out) 76 to 1 SCA MANAGER SLOW CONTROL WriteRead TEST DAC Discri inhibit BUFFER AFTER+: Mode of operation Trigger_out Discri_in Discri_out Hit_channel Trigger_out Write_SCA Read_Address_hit channel Reset Read_SCA Data_SCA_out Asic management (local or global) SCA read: READ & CK read SCA write: Write & CK write Slow control: Din, Dout, CK, CS Test: DAC DAC ADC control Trigger control: multiplicity & detection Reset: hit_channel register Reset SCA_in Channel i Stop Sampling: on external or local Trigger SCA write address read SCA read SCA write

4. ACTAR Meeting Santiago de Compostela March 11, 2008 4 AFTER+ Requirements: Charge measurement Charge Range 3 charge ranges 120fC [750keV], 1pC [6.25MeV] & 10pC [62.5MeV] Adjustable / channel Charge Measurement Output dynamic range: 2V (differential); match the ADC specification [12-bit ADC AD9229] I.N.L: < 2% Peaking Time 16 values: 50ns to 1µs Adjustable / chip Charge Resolution Configuration: Charge Range:120fC; Peaking Time: 200ns; Cin Asic < 30pF asked: < 600 e- rms; possibility: < 850 e- rms.

5. ACTAR Meeting Santiago de Compostela March 11, 2008 5 AFTER+ Requirements: SCA SCA memory cells 511 Sampling frequency 1 MHz to 100 MHz Time Resolution Correlated to the sampling frequency Jitter: < 2ns Reading frequency 20 MHz to 25 MHz

6. ACTAR Meeting Santiago de Compostela March 11, 2008 6 AFTER+ Requirements: trigger Discriminator solution L.E.D Inhibition: / channel Trigger output Current: Σ 72 discriminators OR_hit channel I in I=I in Hit channel 01 I in I=I in Hit channel 02 I in I=I in Hit channel i I in I=I in Hit channel 72 72 x Iin Slow Control Register (2 bits) I in Trigger time resolution The trigger time resolution will be dependent on the input charge, threshold & peaking time value => no spec.

7. ACTAR Meeting Santiago de Compostela March 11, 2008 7 AFTER+ Requirements: trigger Input dynamic range 5% of asic input dynamic range IN.L: < 5 % Threshold value Common DAC: 3 bits + 1 bit of polarity Individual DAC: 4 bits Comment: DACLSB = 0.04% of asic input dynamic range Minimum threshold value Minimum value: ≥ noise Comment: [Preliminary result] 120fC; 30pF; 200ns minimum # 3 keV ( 0.5fC; 0.4 % of asic input dynamic range)

8. ACTAR Meeting Santiago de Compostela March 11, 2008 8 AFTER+ Requirements: Readout Readout frequency 20 MHz to 25 MHz Readout mode: 1 channel means 511 SCA cells All channels [Treadout # 2ms] Hit channels [Treadout # 26µs x nchannel] Specific channels [Treadout # 26µs x nchannel] internal Readout buffer 2 [controlled by slow control] Comment: for all the 4 readout modes ?? Readout mode: 1 channel means 511, 256 or 128 SCA cells Comment: for all the 3 readout modes ??

9. ACTAR Meeting Santiago de Compostela March 11, 2008 9 AFTER+ Requirements: Test Calibration External capacitor; test on 1 channel / 72 “test” 3 internal capacitors (1 / charge range); test on 1 channel / 72 Functional 1 internal capacitor/channel; test on 1, few or all channels

10. ACTAR Meeting Santiago de Compostela March 11, 2008 10 AFTER+ Requirements: Counting rate & Power Counting Rate 1 kHz max. [CENBG] Power consumption < 10 mW / channel

11. ACTAR Meeting Santiago de Compostela March 11, 2008 11 AFTER+ Requirements: Conclusion The design of the chip could be started if all the requirements are defined, approved and fixed. Don’t forget that this chip is only one element of the global readout electronic. Generally, the specifications for the asic and the global electronic architecture are defined in the same time.