1. Development of novel R/O electronics for LAr detectors 6.10.2006 Max Hess Controller ADC Data Reduction Ethernet 10/100Mbit Host Detector typical block diagram for R/O electronics Amplifier

2. Preamplifier for Dark Matter Experiment (ETHZ) Detector: 2 stages LEM ( Large Electron Multiplier ) LEM Gain = 100 / stage  1 electron produce a Q nom = 10 4  1.6  10 -19 C = 1.6 fC Gain = 40 mV / fC Charge amplifier 4 FET‘s in parallel Shaper V ADC ADC C F = 1 pF CDCD RDRD RIRI +-+- CICI R F = 470 M  R D  C D = 1.8  s R I  C I = 0.6  s Noise = 2.1 mV rms V ADC input signal: 200 nA  50 ns = 10 fC 6.10.2006 Max Hess

3. Argon Tube Signal pulse width & charge in one pad in function from the trace angle p = 10 mm trace d pad  s pulse width: t p = d / v drift = p / (v drift  cot  ) signal charge: Q S = Q nom  p  s = Q nom  p / cos  v drift signal current: I S = Q S / t p Pad dimensions: 10 mm x 10 mm v drift = 2 mm/µs @ E drift = 1 kV/cm LEM Gain = 100 1 MIP produces 6000 e - /mm in LAr  Q nom = 100  6000  1.6  10 -19 C = 100 fC/mm 6.10.2006 Max Hess

4. Values for simulation  d [mm] s [mm] t p [  s] Q S [pC] I S [nA] * 0°010.05010 - 3 1.002010 3 30°5.711.52.851.15403 45°10.014.15.001.41282 60°17.320.08.652.00231 89°600.0600.1300.0060.01200 * theoretical: t p  0 and I S  ∞ p = 10 mm trace d pad s v drift  6.10.2006 Max Hess

5. Preamplifier for Argon Tube Transimpedance Amplifier 1 FET Amplifier with lo- and hi-pass filter V ADC ADC C F = 0.1pF CDCD RDRD RIRI +-+- CICI R F = 1 M  Gain = 5.3 mV / nA R I  C I = 0.7  s R D  C D = 1 ms Noise = 400  V rms input signal: 2 uA / 50 ns input signal: 20 nA / 10  s V ADC 6.10.2006 Max Hess

6. Preamplifier for Argon Tube with Op Amp Op Amp AD8655 Linear Amplifier with BW limiting C F = 2.2pF C2C2 R2R2 R1R1 +-+- C1C1 R F = 330 k  R 1  C 2 = 0.7  s R 2  C 2 = 0.7  s +-+- Transimpedance Amplifier V ADC ADC Noise = 860  V rms Gain = 3.5 mV / nA input signal: 2 uA / 50 ns input signal: 20 nA / 10  s V ADC 6.10.2006 Max Hess

7. DAQ box 8 front-end boards 19“ case Block diagram for R/O electronics Ethernet 10/100Mbit Host other DAQ subsystems Flat cables from detector shortest possible: - cable capacitance - noise from outside 256 channels 8 Serial links length max. 10 meter Embeded PC ADC Data Reduction 32 channels ADC MUX 6.10.2006 Max Hess Clock module one for all DAQ system electrically isolated System ground inside the detector

8. DS92LV16 Front-end board ADC 1 SHIFT REG REG MUX 12 1 SHIFT REG REG Preamplifier modules interchangeable for LArDM, ArgonTube, etc. CODER SERIALIZER 16 DE- SERIALIZER CONTROL LOGIC rclk : 2 sclk CS* (16) CODER: create DC-balanced signal code ( 3  4B5B-code) MUX: 32 ADC channels + 1 channel for status (12) to DAQ from DAQ 720 Mb/s electrically isolated CS*: ADC conversion start (1MS/s) sclk: sample clock = 20 MHz rclk: Readout clock = 40 MHz 32 channels 12 FPGA Altera EP1C3T144C8 ADC 6.10.2006 Max Hess

9. Front-end board Ethernet connector serial link to DAQ board 32 ADC‘s ADC121S101 Resolution: 12 bit Sample rate: 1 MS/s Full scale: 3.2 V 2 amplifier / print 100 mm input connector for 32 channels (68 pole flat cable) Serializer/Deserializer NS DS92LV16 Multiplexer FPGA Altera EP1C3T144C8 6.10.2006 Max Hess

10. Front-end case input connector for 32 channels (68 pole flat cable) 8 Front-End modules = 256 channels / case 3 HE = 133 mm 6.10.2006 Max Hess Ethernet connector serial link to DAQ board

11. DS92LV16 Data reduction EXTERNAL CLOCK MODULE one for all DAQ system INPUT FIFO rclk: Readout clock = 2 x ADC clock CS*: ADC conversion start DE- SERIALIZER 16 SERIALIZER rclk CS* circular buffer logic for input memory signal comparator data reduction logic from input memory to output FIFO watch for time stamp generation to Front-end from Front-end 720 Mb/s rclk INPUT MEMORY OUTPUT FIFO ext. trigger in signal detect out FPGA watch clock 16 slow control BUS to Embeded PC and other data reduction boards 6.10.2006 Max Hess

12. Block diagram for data reduction (draft) INPUT BUFFER (SRAM) DATA REDUCTION LOGIC OUTPUT FIFO (DRAM) SIGNAL DET. OUT 1618 DATA 16 MEMORY CONTROLLER addr INPUT FIFO WRITE ADDRESS COUNTER READ ADDRESS COUNTER TRIGGER ADDRESS FIFO I / O CONTROLLER MUX 16 : Altera Cyclone FPGA family with tacc < 12ns it‘s possible to write 32 words and read 48 words in 1µs DELAY FIFO A-B A B COMP TRIGGER DELAY COUNTER WATCH (resolution 1us) THRESHOLD EXTERN TRIGGER INPUT each channel use 1 circular buffer with 2 sectors = 2 x 4096 x 16 bit  total used memory = 4 Mb CLOCK 80 MHz 16 bus to embeded PC from serial link to serial link, slow control 6.10.2006 Max Hess

13. Organisation of input buffer pre trigger time SD write address pointer read address pointer SD: signal detected one independend circular buffer for each channel with two sectors = 2 x 4096 x 16 bit sector A sector B 6.10.2006 Max Hess

14. Data reduction by frame building n post n pre Frame 1 n pre Frame 2 n post digital comparator threshold 6.10.2006 Max Hess t1 registration of possible data during 4095  s = 4095 samples n samples over threshold absolute time  t2 n post n pre n post digital comparator threshold t3 Frame

15. Summary Ethernet 10/100Mbit data reduction Front-end modul amplifier ADC serial link serial link 6.10.2006 Max Hess - ASIC Amplifier Higher number of channels per board Lower power consumption Lower price per channel up to 100‘000 - The system is adaptable for different event rates, variable number of data reduction boards per embeded PC Future design: - ADC with higher sample rate Better time resolution (if needed) - Optical link Longer possible distance from the detector to the DAQ electronic Higher bandwidth - High flexibility for signal conditioning - Optimized for development time to price per channel (for small systems) Actual design: - DAQ Logic Data reduction logic and embeded processor in the same FPGA ( Altera Stratix, Cyclone familly) DAQ box embeded PC