complementary metal–oxide–semiconductor Isolation Technology: Part 2 Ramzan Mat Ayub; SATF 2005 CMOS complementary metal–oxide–semiconductor Isolation Technology: Part 2

LECTURE OBJECTIVES Understand the basic operation of MOS Capacitor Ramzan Mat Ayub; SATF 2005 LECTURE OBJECTIVES Understand the basic operation of MOS Capacitor Able to calculate the Threshold Voltage for MOS Capacitor and Transistor Understand why isolation is needed in CMOS process Understand the isolation requirements and related design rules Able to describe in terms of wafer cross section, the process steps for Semi Recessed LOCOS, Fully Recessed LOCOS, STI and several advanced isolation structures formation.

Standard CMOS Process Flow Ramzan Mat Ayub; SATF 2005 Standard CMOS Process Flow Main Process Modules (CMOS 1P2M 3.3V) Wells Formation Active Area Definition Device Isolation (LOCOS) Vt Adjust Polygate Definition Source & Drain Formation Pre Metal Dielectrics Deposition (PMD) Contact Definition Metal-1 Deposition & Patterning Inter-Metal Dielectrics Deposition (IMD) Via Definition Metal-2 Deposition & Patterning Passivation Pad Definition FRONT END PROCESS (creating an electrically isolated devices) BACK END PROCESS (connecting the devices to form the desired circuit function.) Full integration may require 300-500 process steps

NWELL PWELL L W POLY A B B’ A’ n+ n+ p+ p+ n+ n+ p+ p+ n+ n+ p+ p+ n+ Ramzan Mat Ayub; SATF 2005 PWELL NWELL A L n+ n+ p+ p+ n+ n+ p+ p+ W n+ n+ p+ p+ n+ n+ p+ p+ B B’ A’ POLY

Device Cross Section Device with the similar polarity – simpler Ramzan Mat Ayub; SATF 2005 Device Cross Section Device with the similar polarity – simpler NMOS NMOS n+ n+ n+ n+ p-well CROSS SECTION ALONG A TO A’ LINE

Ramzan Mat Ayub; SATF 2005 Device Cross Section Device with the different polarity – more complicated NMOS PMOS n+ n+ p+ p+ p-well n-well n or p-substrate CROSS SECTION ALONG B TO B’ LINE

MOS Device Isolation Requirements Ramzan Mat Ayub; SATF 2005 MOS Device Isolation Requirements MOS Transistors are isolated as long as; source-substrate and drain-substrate pn junctions are held at reverse bias unwanted channels are prevented from forming among adjacent devices Field transistor DRAIN SOURCE NMOS#1 NMOS#2

MOS Device Isolation Requirements Ramzan Mat Ayub; SATF 2005 MOS Device Isolation Requirements Electric circuit in VLSI technology is implemented by connecting isolated devices through specific conducting path. To fabricate monolithic ICs, electrically isolated devices must be created in the silicon substrate and connected at a later stage Improper isolated device will result: total circuit failure high leakage (large dc power dissipation) noise margin degradation voltage shift, cross talk between transistors and etc.

MOS Device Isolation Requirements Ramzan Mat Ayub; SATF 2005 MOS Device Isolation Requirements The challenge is VLSI device only allows single transistor leakage < 10 pA/um). On the other hand, process integration imposed a stringent requirement on the isolation technology: spacing between actives should be as small as possible to produce the surface topography as planar as possible isolation process module must be simple to implement and easy to control

MOS Device Isolation Requirements Ramzan Mat Ayub; SATF 2005 MOS Device Isolation Requirements VTF is the threshold (minimum) voltage to turn on the parasitic MOS (field transistor) VTF is normally at least 8 V above supply voltage to ensure less than 1 pA/um between isolated MOS device VTF equation: 2 methods of increasing the VTF; making a thicker field oxide Increase the doping beneath field oxide (channel stop implant)

MOS Device Isolation Requirements Ramzan Mat Ayub; SATF 2005 MOS Device Isolation Requirements Field transistor M-1 DRAIN SOURCE NMOS#1 NMOS#2

MOS Device Isolation Characterisation Ramzan Mat Ayub; SATF 2005 MOS Device Isolation Characterisation Test Structures for NMOS Isolation poly poly n+ n+ n+ n+ Aluminum

MOS Device Isolation Characterisation Ramzan Mat Ayub; SATF 2005 MOS Device Isolation Characterisation The purpose; To find the VTFiso : The gate voltage at which the maximum allowable leakage current arise To find the optimum n+ to n+ spacing Gate voltage (VTFiso) at drain current @ 1nA or 1pA, at VD = Vcc, is measured VTFiso is plotted against n+ to n+ spacing to find the optimum n+ to n+ at certain VDS values

MOS Device Isolation Characterisation Ramzan Mat Ayub; SATF 2005 MOS Device Isolation Characterisation VTFiso Volts Channel current 25 0.1 u A 20 1 n A 15 10 p A 10 5 0.5 1 1.5 2 2.5 3 3.5 4 n+ to n+ spacing in micron

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Grow and etch thick oxide (1970) Semi recessed LOCOS (1980) Basic LOCOS Poly buffered SILO and etc Fully recessed LOCOS (1980) Side Wall Mask Isolation (SWAMI) Self Aligned Planar Oxidation (SPOT) FUROX (Fully Recessed Oxide) Shallow Trench (STI) (1990) SOI + STI (2000)

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Grow and Etch Technique substrate b) Pattern and etch substrate a) Grow thick oxide c) S/D diffusion

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Grow and etch (used until late 70s) Thick oxide is grown thermally in the furnace Wafer is patterned and etch Disadvantages Sharp corners, difficult to cover in the latter process steps Channel stop must be implanted before oxide is grown (active to be aligned with channel stop region – low packing density)

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques LOCOS Isolation Technology oxidation oxidation nitride removal nitride removal a) Semi recessed LOCOS b) Fully recessed LOCOS

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Basic Semi-recessed LOCOS Process Step-1: Pad Oxide Layer Wafer is cleaned using RCA cleaning technique 200-500A SiO2 (called pad or buffer oxide) is thermally grown The function of this oxide is to cushion the transition of stress between the silicon substrate and the subsequently deposited nitride. Silicon substrate

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Basic Semi-recessed LOCOS Process Step-2: Silicon Nitride Layer 1000-2000A thick layer of CVD silicon nitride is deposited. The function of this nitride is as mask to the oxidation process. Silicon nitride is very effective as oxidation mask because oxygen and water vapor diffuse very slowly through it, preventing oxidising species from reaching the silicon surface under the nitride. Silicon nitride however exhibiting a very high tensile stress (1010 dynes/cm2), hence used with minimal thickness.

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Basic Semi-recessed LOCOS Process Step-3: Photolithography-Active Area Definition To define the active area (where the transistors to be put) Silicon substrate Silicon substrate

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Basic Semi-recessed LOCOS Process Step-4: Nitride Etch To cover the active regions, expose areas to form LOCOS Silicon substrate

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Step-5: Channel stop implant To create a channel stop doping layer under Field Oxide. In NMOS circuit, a p implant (boron, 60-100 keV) is used, while in PMOS, arsenic is used. PR is removed after the implant Silicon substrate

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Step-6: Grow Field Oxide Field oxide is thermally grown by wet oxidation at temperatures around 1000C to the thickness 8000-10,000A. Oxide will grows where there is no masking nitride, but at the nitride’s edges, some oxidation occurred. This caused the nitride’s edges to lift. Because of the shape, this structure is called bird’s beak. Silicon substrate

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques The bird’s beak is a lateral extension of the field oxide into the active area of the devices. For a typical 8000A LOCOS, bird’s beak ~ 5000A. Limiting factor for the usage of LOCOS. 8000 A FINAL ACTIVE AREA BIRD’S BEAK 5000 A ORIGINAL MASK

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Step-7: Strip Masking Nitride Layer Oxynitride etch (200-300A top layer of nitride) – deglaze process Wet hot phosphoric process to remove nitride (good selectivity to oxide) Tricky process, deglaze process must be carefully characterised. Silicon substrate

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Step-8: Regrow and strip sacrificial oxide Kooi et al discovered that a thin layer of silicon nitride can form on the silicon surface (pad oxide – silicon interface). This nitride spot is called white ribbon or Kooi Effect and must be removed to prevent defect from occurring when growing gate oxide. This can be done by growing sacrificial gate oxide to consume the nitride spots, strip sacrificial oxide and regrow a good gate oxide

After stripping masking nitride and pad oxide Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques KOOI Effect Si3N4 After stripping masking nitride and pad oxide SiO2 SiO2 NH3 Si3N4 - White ribbon Si3N4 + 6H2O → 3SiO2 + 4NH3 3Si + 4NH3 → Si3N4 + 6H2 Si Si

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Factors Affecting Bird’s Beak Length and Shape Pad oxide thickness - Lateral oxidation can be reduced by using a thinner pad oxide, leading to a shorter bird’s beak. Pad layer composition – CVD oxynitride Silicon crystal orientation – shorter bird’s beak in <111> compared to <100> Field oxide process temperature – Shorter with higher oxidation temperature. Thickness and mechanical properties of nitride layer – the thicker the nitride, the shorter the bird’s beak Mask stack geometry – depends on the shape and size of the structures

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques SEM picture of Semi-Recessed LOCOS

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Advanced Semi-Recessed LOCOS Process A) Poly Buffered LOCOS Based on the fact that a thinner pad oxide will produce a shorter bird’s beak. Usual pad oxide is replaced with a polybuffered layer; poly 500A:oxide 100A Thicker nitride is used to suppress the bird’s beak more, 1000 – 2500A B) Sealed Interface LOCOS Reduce the bird’s beak by depositing nitride layer directly onto the silicon. Lateral diffusion of oxidants is suppressed better, resulting a shorter bird’s beak.

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Basic Fully-recessed LOCOS Process Step-1: Pad Oxide Layer Wafer is cleaned using RCA cleaning technique 200-500A SiO2 (called pad or buffer oxide) is thermally grown The function of this oxide is to cushion the transistion of stress between the silicon substrate and the subsequently deposited nitride. Silicon substrate

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Step-2: Silicon Nitride Layer 1000-2000A thick layer of CVD silicon nitride is deposited. Silicon substrate

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Step-3: Photolithography-Active Area Definition To define the active area (where the transistors to be put) Silicon substrate

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Step-3: Photolithography-Active Area Definition To define the active area (where the transistors to be put) Silicon substrate

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Step-4: Nitride Etch, Oxide Etch, Silicon Etch To cover the active regions, expose areas to form LOCOS Silicon substrate

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Step-5: Channel stop implant To create a channel stop doping layer under Field Oxide. In NMOS circuit, a p implant (boron, 60-100 keV) is used, while in PMOS, arsenic is used. PR is removed after the implant Silicon substrate

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Step-6: Grow Field Oxide Field oxide is thermally grown by wet oxidation at temperatures around 1000C to the thickness 8000-10,000A. Oxide will grows where there is no masking nitride, but at the nitride’s edges, some oxidation occurred. This caused the nitride’s edges to lift. Because of the shape, this structure is called bird’s beak. BIRD’S HEAD BIRD’S BEAK

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Step-7: Strip Masking Nitride Layer Step-8: Regrow and strip sacrificial oxide

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques SEM picture of Fully-Recessed LOCOS

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques A) Advanced Fully-Recessed LOCOS Process Step 2: Oxide / Nitride Etch and Silicon Etch Sloping sidewall, help to reduce the stress during oxidation Silicon substrate

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Advanced Fully-Recessed LOCOS Process Step 3: Second layer of pad oxide and nitride. After that grow an oxide layer Silicon substrate

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Advanced Fully-Recessed LOCOS Process Step 4: Etch Oxide, Etch Nitride Silicon substrate

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Advanced Fully-Recessed LOCOS Process Step 5: Field Oxidation Silicon substrate

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques Advanced Fully-Recessed LOCOS Process Step 6: Nitride / Oxide strip LOCOS Active Silicon substrate

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques B) Self Aligned Planar Oxidation Technology (SPOT) Another modified fully-recessed LOCOS to eliminate the bird’s beak and head. Conventional semi-recessed LOCOS is grown using high pressure oxidation. The LOCOS then removed using BOE SiO2

Overview on CMOS Isolation Techniques Ramzan Mat Ayub; SATF 2005 Overview on CMOS Isolation Techniques B) Self Aligned Planar Oxidation Technology (SPOT) Second pad oxide is grown, followed by deposition of a second CVD nitride Nitride and oxide then anisotropically etched. Second LOCOS is then grown using High Pressure Oxidation

Trench Isolation Technology Ramzan Mat Ayub; SATF 2005 Trench Isolation Technology 4 major applications Locos replacement for isolation within the well (STI) Isolation in bipolar (Moderate Trench) Latch prevention in CMOS (Moderate Trench) Trench capacitor in DRAM (Deep Trench) 3 categories Shallow trench <1 um Moderate 1-3 um Deep >3um deep Advantages - Increase the packing density tremendously Disadvantages Complex to fabricate, very expensive machines Poor uniformity, Low throughput

Trench Isolation Technology Ramzan Mat Ayub; SATF 2005 Trench Isolation Technology Trench etched CVD oxide deposited Oxide polished to surface by CMP

Silicon On Insulator (SOI) Ramzan Mat Ayub; SATF 2005 Silicon On Insulator (SOI) Completely isolate the transistor on silicon surface from the bulk silicon substrate. Tremendously increase the packing density of IC chip Mainstream isolation technology for high performance ICs for feature size below 0.13um process technology Normally coupled with Copper Interconnect Technology and Low-k Interlevel Dielectric.