1. Chapter 1
&
Chapter 3

2. Circuit Under Design
From Rabaey 2003

3. Inverter Cross-Section
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

4. Biasing Points (G, D and S) How about the bulk (substrate)?
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

5. With Substrate Contacts
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

6. Masks
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

7. Photomask in Operation
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

8. Patterning of SiO2 Chemical or plasma etch Si-substrate
Hardened resist
SiO 2
(a) Silicon base material
Si-substrate
Photoresist
SiO 2
(d) After development and etching of resist,
chemical or plasma etch of SiO
Si-substrate 2
(b) After oxidation and deposition
Hardened resist
of negative photoresist
SiO 2
Si-substrate
UV-light
Patterned
(e) After etching
optical mask
Exposed resist
SiO 2
Si-substrate
Si-substrate
(f) Final result after removal of resist
(c) Stepper exposure
From Rabaey 2003

9. CMOS Process at a Glance
Define active areas
Etch and fill trenches
Implant well regions
Deposit and pattern
polysilicon layer
Implant source and drain
regions and substrate contacts
Create contact and via windows
Deposit and pattern metal layers
From Rabaey 2003

10. P-Type Substrate and N-Well
PMOS devices
go here
P-type substrate
NMOS devices
go here
N-well mask
slides on mask sequence by Jay Brockman – Univ. notre Dame
From Rabaey 2003

11. Active Area deposited nitride layer active mask defines
p-type and n-type
mosfet locations
(drain-gate-source)
From Rabaey 2003

12. Field Oxide Growth Thick field oxide electrically isolates transistors
Nitride prevents field oxide growth
Thin gate oxide grown after nitride removed o2 o2 o2 o2 o2 o2 o2
gate oxide
field oxide
SiO2 formation consumes Si
Si-SiO2 interface below original Si surface
From Rabaey 2003

13. Polysilicon Gate
poly mask
added to layout
From Rabaey 2003

14. P-Select Mask and N-Type Source/Drain Implant
p-select covers p-type source/drain regions
select mask must overlap active areas
n-type ion implant creates n-type source/drain regions
high temperature anneal repairs silicon lattice and causes diffusion of implanted ions
From Rabaey 2003

15. N-Select Mask and P-Type Source/Drain Implant
p-type implant
finished mosfets
both select masks added
From Rabaey 2003

16. Improving Drain and Source
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

17. Contact Cuts
Thin oxide
Field oxide
From Rabaey 2003

18. Metal 1
non-planar surface
From Rabaey 2003

19. Via 1 and Metal 2
Multilevel interconnect fabrication processes planarize between layers (expensive)
MOSIS SCMOS does not allow stacked vias
From Rabaey 2003

20. Sharp Etch Profile for Metal
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

21. Metallization Cross-Section
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

22. Substrate Contacts
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

23. p+ Substrate Contact
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

24. Final Steps w/ Substrate Contact
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

25. An Inverter Layout
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

26. A Standard Cell Layout Why l ?
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

27. Stick Diagram Dimensionless layout entities Only topology is important
Final layout generated by “compaction” program
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

28. Color Stick Diagram 1 V 3 In Out GND Dimensionless layout entities
Stick diagram of inverter
Dimensionless layout entities
Only topology is important
Final layout generated by “compaction” program
From Rabaey 2003

29. Hypothetical 90nm Tech. Design Rules
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

30. Hypothetical 90nm Technology
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

31. 90 nm Technology Design Example Design Rules 0,15mm 0,1mm 0,15mm
l = 0,03mm
0,15mm
Design Rules

32. Design Rules are Followed
Alignment Mark
Design should be Fine !!
l = 0,03mm

33. Active and Poly Masks
Poly Mask
Active Mask

34. Fabricated Transistor (Under Misalignment of 0.06 mm)
Alignment Marks
Transistor Still Correct !!
l = 0,03mm
Design Example

35. Design Rules are Not Followed
Alignment Mark
Design in Danger !!
l = 0,03mm

36. Active and Poly Masks- 2
Closer
Poly Mask
Active Mask

37. Fabricated Transistor (Under Misalignment of 0.06 mm)- 2
Alignment Marks
Transistor with Changed W and L !!
l = 0,03mm

38. Design Rules- 1 Interface between designer and process engineer
Guidelines for constructing process masks
Unit dimension: Minimum line width
scalable design rules: lambda parameter
absolute dimensions (micron rules)
Attention: usually, l is half of smallest allowed transistor channel length (L)

39. Design Rules- 2
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

40. Routing Tracks
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

41. nMOS and pMOS Spacing
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

42. MOSIS Design Rules mosis.com
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

43. Some Technologies by MOSIS
Observe l is the best approximation to the half of the feature size
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

44. MOSIS Design Rules Listing
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

45. MOSIS Design Rules Listing
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

46. Hypothetical 90nm Tech. Design Rules 3-46
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.
3-46

47. Hypothetical 90nm Technology
Copyright © 2005 Pearson Addison-Wesley. All rights reserved.
3-47