1. IC Manufactured
Done by:
Engineer Ahmad Haitham

2. The First Computers: BDE&ENIAC
Vacuum Tube 1946
The Babbage Difference Engine
(1832)

3. The Transistor Revolution
First transistor
Bell Labs, 1948
ECL 3-input Gate
Motorola 1966
1st IC: Bipolar logic
1960’s

4. Intel 4004 and Pentium (IV) Ps
1971
1K transistors
1 KHz operation
2000
10M transistors
1 GHz operation

5. Let’s Start The Story !!!

6. The Silicon Cylinder called Ingot (1 or 2 Meters in Length)
Can be Sliced into Hundreds of Smaller Circular Pieces Called Wafers
Each Wafer Yields Hundreds or Thousands of Integrated Circuits

7. Single die
Wafer
(20 – 30) cm diameter
(0.35 – 1.25) mm thick

8. The surface is free of Scratches and imperfections

9. Die or IC Fabrication There are 20 to 30 major steps.
Each step require five or more operations.
Hence, There are 100 to 200 distinct operations to produce a complete IC.
Today, IC chip may be up to 30mm on each edge and contains 100 million devices (Transistor, Diode, Resistor,…..etc)

10. Some of operations

11. Oxidation: High temperature exposure of silicon to oxygen to form SiO2.
Etching: Removal of undesired material with the use of chemical liquid or ionized gas etchant.
Diffusion: Doping process to form n-type or p-type material by high temperature exposure to donor or acceptor impurities

12. Ion Implementation: High-energy bombardment of silicon with donor or acceptor ions from certain accelerator
Chemical Vapor Deposition: Material such as metal or oxide are deposited out of a gaseous mixture. Metal can also be deposited using sputtering.

13. The basic flow in the IC fabrication process

14. In the PC running certain software
Draw a schematic that shows the layout
of the geometric patterns that implement
The transistors and interconnection

15. The patterns are converted to a set of masks, one for each major step in
The fabrication process.
Masks are glass plates with patterns specify the information that will be
Printed to the IC in a given step

16. Photolithography

17. What is Photolithography
What is Photolithography? Process of transferring geometric shapes on a mask to the surface of a silicon wafer

18. MOSFET Photolithography

19. Grow SiO2
Deposit polysilicon layer

20. Wafer is then coated with a polymer which is sensitive to ultraviolet light called a photoresist

21. There are two basic types of Photoresists, Positive and Negative.
Positive Photoresists becomes soluble when exposed with UV light.
Negative Photoresists becomes polymerized, and more difficult to dissolve when exposed with UV light.

22. mask, which will be typically be a chromium pattern on a glass plate
Ultraviolet light is then shone through the mask onto the photoresist
Positive photoresist

23. The photoresist is then washed by developer, The resist exposed with UV light will be dissolved

24. Etch the unwanted polysilicon.
Etching is the process where unwanted areas are removed by either dissolving them in a wet chemical solution (Wet Etching) or by reacting them with gases in a plasma to form volatile products (Dry Etching)

25. Remove the photoresist.
The polysilicon pattern is done.

26. Implant Source & Drain regions of the MOSFET

32. Implant dopant ions through patterned openings in photoresist

34. Repeat metal layers.

35. Create contact windows, deposit & pattern Metal layer

37. Fabrication Process for DSM CMOS
1- Define Well areas and transistor regions.
NMOS is diffused in a p-type well
PMOS is diffused in a n-type well
2- Trenches are dug out of the silicon between the wells
3- Oxide is deposited in these stenches using the chemical
vapor deposition process (CVD).

38. 4- Define the gate region. Clean thermal
oxide is grown in the transistor area by
exposure to oxygen in a furnace.

39. 5- Define the poly gate. Again a polycrystalline silicon layer is deposited by CVD
6- Undesired poly and oxide are removed by
chemical etching or by plasma (Reactive gas)

40. 7- Form source/drain regions
7- Form source/drain regions. Ion implementation is used for the doping step.

41. 8- Depositing silicide material to lower the resistance since because the source, drain and gate materials have relatively high resistance which may slow down the operation of the transistor..

42. IC Fabrication

43. Layout and Design Rules

45. The minimum feature size is L, the channel length of the MOSFET.
Scalable rules (abstract dimensional unit , usually half of minimum feature size)
The minimum feature size is L, the channel length of the MOSFET.
MOSIS SCMOS

46. In general, there are three main classes of design rule specifications
In general, there are three main classes of design rule specifications. These are
Minimum Width. Which is the smallest dimension permitted for any object in the layout drawing
Spacing. Which is the smallest distance permitted between the edges of two objects.
Surround. This apply to objects placed within larger objects (such as contacts).
Every layer has minimum width and minimum spacing value, while surround are specified as required.

47. SCMOS Layout Rules - NWell

48. SCMOS Layout Rules - Active

49. SCMOS Layout Rules - Poly

50. SCMOS Layout Rules – Select

51. SCMOS Layout Rules - Contact to Poly & Contact to Active

52. SCMOS Layout Rules - Metal1

53. SCMOS Layout Rules - Via

54. SCMOS Layout Rules - Metal2

55. NMOS Layout

56. PMOS Layout

57. CMOS Inverter Circuit

58. STICK DIAGRAM
Vdd = 5V
pMOS
N MOS
Vin

59. Stick Diagrams In
Out V DD
GND A
Out V DD
GND B
Inverter
NAND2

60. The steps to draw the layout of the CMOS inverter using
L-EDIT SOFTWARE

72. * NODE NAME ALIASES
* = VSS (-10, )
* = VDD (-12.5,43.5)
* = VOUT (43.999,50.5)
* = VIN (23.499,51.5)
Cpar1 1 0 C= f
Cpar2 2 0 C= f
Cpar3 3 0 C= f
M PMOS L=0.6u W=3u AD=7.2p PD=10.8u AS=7.2p PS=10.8u
M NMOS L=0.6u W=1.2u AD=3.96p PD=8.4u AS=3.96p PS=8.4u
.END