XILINX CPLDs The Total ISP Solution

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Presentation transcript:

XILINX CPLDs The Total ISP Solution

Building CPLDs For Total Product Life Cycle Support XC9500/XL CPLDs Provides Total Solution Built for ISP & Superior Pin-Locking Uses Advanced Flash Technology Complete ISP/ATE Software Support Field Upgrades Proto- typing Product Life Cycle Manufacturing & Test

XC9500/XL CPLDs Key Features Flexible ISP architecture with superior pin-locking XC9500: 5v family XC9500XL: 3.3v family High performance: 4ns pin-to-pin (XL) Full IEEE 1149.1 JTAG 5v/3.3v/2.5v I/O compatibility Highest reprogramming reliability Space-efficient packaging Low cost

Xilinx CPLD Process Leadership Non-Volatile Year used in Year used in SPLD/CPLD Technology Memories SPLD/CPLD Pioneer Bipolar Fuse 1973 1978 MMI (AMD) EPROM 1979 1984 Altera EP-series 5V EEPROM 1986 1991 Lattice ispLSI 5V FLASH 1990 1995 Xilinx XC9500 Xilinx is the world leader in FLASH process technology for CPLDs! The FastFLASH process uses the same device structures as the FLASH memories, which provides benefits in large economies of scale for R&D, and benefits in cost, speed, and foundry availability into the future. The process also allows intrinsic product benefits, including more routing switches in the same chip area, higher programming reliability (measured by endurance), and lower cell capacitance. As has been consistent since the 1970’s, PLD processes have historically leveraged the high-volume memory processes as process drivers, starting with the bipolar fuses. Going forward, FLASH process has become THE standard for non-volatile memory processes, and will become the standard for PLDs as well! 3.3V FLASH 1993 1998 Xilinx XC9500XL 7

FLASH Technology Enables Rapid Die Size Reduction

CPLD Price Leadership Without Compromises Flexible ISP tPD = 4ns (‘99); 2.5ns (‘02) Best Pin-Locking Industry Standard JTAG 2.5V (0.25u Flash) in 1999 $20 288 Macrocells $9 $ (unit price) $5.75 144 Macrocells Xilinx CPLDs will take full advantage of the leadership processing capabilities and small die sizes that result from our Flash process. The Flash process allows for constant die size reductions which, in turn, provide our customers with the best cost reduction path for the coming years. Three examples are shown to highlight the cost/price benefits from our Flash process migrations. Today, the 5v and 3.3v product are represented in this graph. From the year 2000 and on, prices represent the 3.3v (XL) and 2.5v (XV) products. Both the XL at 0.35 micron and the XV at 0.25 micron provide the optimum performance/price solution from the year 2000. Low pricing is key to our customer base but we give them the attractive price along with industry-leading product features like speed, pin-locking (pioneered and proven to be critical to ISP users by Xilinx) and full-up, industry standard JTAG. $3.95 $1.20 36 Macrocells $0.80 * Prices are based on 100Ku+, slowest speed grade, lowest cost package

Chip Scale Packaging Leadership Supports high-growth market segments: Communications, Computers, Consumer New 48-pin CSP: 1/3 size of the VQ44 Uses standard IR techniques for mounting to PC board

New XC9500XL 3.3V Family XC9536XL XC9572XL XC95144XL XC95288XL Macrocells 36 72 144 288 Usable Gates 800 1600 3200 6400 tPD (ns) 4 5 5 6 fSYSTEM 200 178 178 151 Packages (Max. User I/Os) 44PC (34) 64VQ (36) 48CS (36) 44PC (34) 64VQ(52) 100TQ (72) 48CS (38) 100TQ (81) 144TQ (117) 144CS (117) 144TQ (117) 208PQ (168) 352BG (192) The family is planned with 6 devices in the most popular macrocell densities. Note the full complement of pin-compatible package options. The family will become available starting 2H98, beginning with the XC95144XL. After that, the ‘72XL and ‘36XL will become available. BGA CSP 9

XC9500 5V Family XC9536 XC9572 XC95108 XC95144 XC95216 XC95288 Macrocells 36 72 108 144 216 288 Usable Gates 800 1600 2400 3200 4800 6400 tPD (ns) 5 7.5 7.5 7.5 10 15 fSYSTEM 100 83 83 83 67 56 Max. User I/Os 34 72 108 133 166 192 Packages (Max. User I/Os) 44VQ (34) 48 CSP(34) 44PC (34) 84PC (64) 100TQ (72) 100PQ (72) 84PC (69) 100TQ (81) 100PQ (81) 160PQ (108) 160PQ (133) 208HQ (168) 352BG (192) 208HQ (166) 352BG (166)) The family as it is today. Many customers are still learning about the Xilinx XC9500 and this foil provides them all the necessary basic information to become familiar with the family quickly. Note: Based on refocused priorities toward 0.5µ and 0.35µ products, the XC95180 is not longer part of the family. All XC95180 designs are easily accommodated by the XC95216, thus simplifying the number of devices and the overall density message without leaving a density gap for our customers.

Productive Implementation Flow for CPLDs Simplified Project Management Implementation Templates for Speed & Density Push Button Design Flows USER BENEFITS Faster Clock Speeds Higher Device Utilization optimized logic/cm2 Industry’s Best Pin-Locking more design flexibility, less risk, lower cost

What’s New In V1.5 CPLDs Evolutionary Logic Algorithms for XC9500 5V CPLDs higher clock frequencies, improved density & faster runtimes Full Support of XC9500XL 3.3V CPLDs Includes “Advance” speed grades for fastest XC9500XL devices Improved Timing Driven CPLD Fitting JTAG Programmer now supports: XC9500/XL CPLDs, Virtex, XC4000E/X/XL, XC5200, SPARTAN/XL FPGAs XC9500/9500XL support in LogiBLOX AllianceCORE CPLD based IP

XILINX CPLDs The total ISP solution Complete support of customer’s Product Life Cycle Industry’s best pin-locking CPLD at lowest price Multiple software solutions to choose from Based on leadership FLASH technology CPLD users are all going to ISP and Xilinx will be “driving” this ISP evolution process with the XC9500. It offers the industry’s best product life cycle support, pin-locking, architecture and software to enable this evolution to take place. No other competitor offers this complete of a solution to the CPLD market. And now, with this roadmap, CPLD users can now see the Xilinx commitment to providing the next generations of CPLD products, all which will be design to fit the users needs.