Analytical Delay and Variation Modeling for Subthreshold Circuits

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Presentation transcript:

Analytical Delay and Variation Modeling for Subthreshold Circuits Sungil Kim and Vishwani D. Agrawal Auburn University Department of Electrical and Computer Engineering {szk0075, agrawvd}@auburn.edu 3/2/2016

Constraint on Power in Modern Electronics Ultra Small Computer / Imager Biomedical Sensor /Monitoring Device Portable / Wearable Device For Low to Moderate Speed Systems: Power Consumption / Management >>> Performance 2

Supply Voltage VDD vs. Power PTM 16-nm LP Vth = 0.68V Drawback: PVT Variations - Process - Voltage - Temperature Ptotal∝ VDD2 3

Scaling Down VDD Below Vth Idea of Subthreshold Circuits: 1971 (Meindl and Swanson) Workability: 1900s – 2000s (Chandrakasan, Blaauw, Sylvester…) PTM 16-nm LP Vth = 0.68V Minimum Energy 4

VDD Scaling Trend ADC: limits exist on VDD scaling, but trend is downward 5

VDD Scaling from ISSCC Analog Trend 6

Necessity of Delay Model and Challenges Accurate delay model => better predict circuit behavior Set the operating region and process corners — essential for extreme environments — military applications (extreme temperature) Used for timing analysis and VLSI design stage Subthreshold Circuits pose challenges — susceptible to PVT (process, voltage, temp) variations — Isat exponentially depends on gate, threshold voltage — reduced Ion / Ioff => Alpha-power model is no longer accurate New delay model for the subthreshold is needed. 7

Review of Alpha-Power MOSFET Model T. Sakurai and A. Richard Newton 8

Previous Research Overview 0 —> 1 Input F. Frustaci, P. Corsonello, and S. Perri, “Analytical delay model considering variability effects in subthreshold domain,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, no. 3, pp. 168–172, 2012. 9

Proposed Subthreshold Delay Model 0 —> 1 Input 10

Parameter Extraction for Alpha-Power MOSFET Model 11

Alpha-Power Delay Model in Subthreshold Region Proposed: Avg. Error ≈ 15% Max. Error ≈ 25% Alpha-Power Avg. Error ≈ 21% Max. Error ≈ 83% PTM 45-nm LP 0 —> 1 Input 12

Alpha-Power Delay Model in Subthreshold Region Max. Error ≈ 466% Proposed Max. Error ≈ 77% PTM 45-nm LP 1 —> 0 Input 13

Simulation Results PTM 16-nm LP Error Alpha-power (red) Proposed (green) Average 39.8% 16.5% Worst 71.1% 33.4% 14

Novelty of Proposed Models Delay Model Verify alpha-power MOSFET model in the subthrehsold region Show ~83% (0->1 input) and ~466% (1->0 input) error by simulating with PTM 45-nm LP model Unlike some of the previous models, consider DIBL effect Variations Model Adding compensation factors to increase the accuracy Simulate the proposed models over broader ranges of VDD Verify on smaller technology node (16-nm) that potentially have more variations than 130-nm or 45-nm models 15

Proposed Voltage Variation Model Compensation Factor 16

Proposed Model Result (1): VDD Variation PTM 16-nm LP Avg. Error = 14.6%, Max. Error = 79.1% 17

Proposed Temperature Variation Model Compensation Factor 18

Proposed Model Result (2): Temp Variation Avg. Error = 6.8%, Max. Error = 37.9% PTM 16-nm LP 19

Proposed Process Variation Model Mainly due to threshold voltage (Vth) variation 20

Proposed Model Result (3): Vth Variation PTM 16-nm LP Monte Carlo 1000 runs Avg. Error = 1%, Max. Error = 6% 21

Effect of Compensation Factor Carefully chosen from the results of previous research Error VDD Variation Temp Variation without with factor Average 27.4% 14.6% 62.1% 6.8% Best 0.4% 0.1% 20.2% Worst 131.7% 79.1% 87.5% 37.9% T. Lin, K.-S. Chong, B.-H. Gwee, J. S. Chang, and Z.-X. Qiu, “Analytical delay variation modelling for evaluating sub-threshold synchronous/asynchronous designs,” in Proc. IEEE Int. NEWCAS, Jun. 20–23, 2010, pp. 69–72. 22

Summary Reviewed power-constrained electronics Explored subthreshold circuit and its advantages Analyzed alpha-power law MOSFET model Review current state-of-the-art analytical delay model Verified delay model via simulation on PTM 45-nm / 16-nm Proposed delay variations models — process variation (Vth) — voltage variation (VDD) — temperature variation Verified models via simulation on PTM 16-nm LP technology — up to 4.31×, 1.29×, and 1.88× PVT variations 23

Questions? Thank you!