1. 26 th International Conference on VLSI January 2013 Pune,India Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal

2. Outline Introduction – Problem Statement Integer Linear Programming (ILP) – ILP: Variable test clock Optimum supply voltage – Results for ASIC Z Future Work Conclusions 10/25/2015© VLSI Design Conference 20132

3. Introduction Technology scaling has led to more cores and increased complexity in SoC devices. – This has resulted in high test data volumes and longer test times. – Reducing test time is one of the major objectives in SoC testing 10/25/2015© VLSI Design Conference 20133

4. Problem Statement Given an SoC with N core tests and a peak power budget, find a test schedule to: – Test all cores. – Maximize concurrency to reduce test time. – Conform to power budget by restricting concurrency. 10/25/2015© VLSI Design Conference 20134

5. An Example – ASIC Z Y. Zorian, “A distributed control scheme for complex VLSI devices,” VTS’93, pp. 4–9. Often used as benchmark for SoC test scheduling. 10/25/2015© VLSI Design Conference 20135 RAM 2 (61,241) RAM 3 (38,213) ROM 1 (102,279) ROM 2 (102,279) RAM 1 (69,282) RAM 4 (23,96) Reg. file (10,95) Random logic 1 (134, 295) Random logic 2 (160, 352) P max = 900 Block (time, power) Blocks of ASIC Z, and their test time (in a.u.) and test power (in mW)

6. An Example – ASIC Z Comparison of existing optimal test schedules for ASIC Z. 10/25/2015© VLSI Design Conference 20136 Test Session Chou et al. [1] Larsson and Peng [2] Test TimeBlocksTest TimeBlocks 169RAM1,RAM3,RAM4,RF160RL2,RL1,RAM2 2160RL1,RL2102RAM1, ROM1, ROM2 3102ROM1,ROM2,RAM238RAM3, RAM4,RF 331300 [1] R. M. Chou et al, “Scheduling tests for vlsi systems under power constraints,” IEEE Trans. VLSI Systems, vol. 5, no. 2, pp. 175–185, 1997. [2] E. Larsson and Z. Peng, “An integrated framework for the design and optimization of soc test solutions,” JETTA Spl. Ed., vol. 18, pp. 385–400, 2002

7. Integer Linear Progam (ILP) Given: – Power budget for SoC, P max – N core tests for an SoC. t i = test time and p i = test power of i th test – K sessions in the test schedule for N core tests. Test time of jth session is, T j = max{t i } Test power of jth session is, P j = ∑ (p i ) 10/25/2015© VLSI Design Conference 20137

8. Variable Test Clock Frequency 10/25/2015© VLSI Design Conference 20138 Selectable clock frequency for each test session. Increasing test clock frequency by a factor f => Test time, and Test power, Proper choice f for each session (ref. to as frequency factor) can optimize overall test time.

9. Objective: Minimize, where Subject to: – Power constraint: – Test completeness constraint: 10/25/2015IEEE SOCC 20129 ILP: Variable Test clock

10. Frequency Factor 10/25/2015© VLSI Design Conference 201310 F j = Frequency factor of j th session. Frequency factor limited by: – P max (Power Constraint) – Max. speed of slowest core in session For simulation, max. clock frequency values assigned to ASIC Z blocks.

11. ASIC Z Results 10/25/2015© VLSI Design Conference 201311 Slower clock Faster clock Nominal clock Prev. Best Optimal Solution

12. Constraints on Frequency Each core’s max. clock rate decided by: – Max. power limit of core (power constraint) – Critical path delay (structural constraint) Both constraints also influenced by V DD. – Power Constraint: – Structural constraint: 10/25/2015© VLSI Design Conference 201312 (also known as Alpha power law)

13. Influence of V DD on Test time Power constrained test: Structure constrained test: An optimal V DD can balance the two constraints. 10/25/2015© VLSI Design Conference 201313

14. Optimal V DD Selection Experiments on ISCAS circuits show upto 62% improvement in test time at optimal V DD [3]. 10/25/2015 © VLSI Design Conference 2013 14 [3] P. Venkataramani and V. D. Agrawal, “Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage.” Proc. VLSID, in press, Jan. 2013. Simulation and experimental test time plots for s298 [3]

15. Optimal V DD Selection for SoC Clock frequency of a test session may be power constrained or structure constrained. – If power constrained, lowering V DD improves test time. – If structure constrained, lowering V DD deteriorates test time. Objective: To find optimal V DD for power constrained test sessions, thereby reduce overall test time. 10/25/2015 © VLSI Design Conference 2013 15

16. ASIC Z Results Revisited 10/25/2015© VLSI Design Conference 201316 Slower clock Faster clock Nominal clock Prev. Best Optimal Solution Saturates at 268.3 time units. Point A Cannot further reduce time by increasing Frequency factor. – Limited by frequency constraints.

17. Assumptions At Point A: – All test session frequencies are power constrained. – Structural constraint limit >> power constraint limit. – Nominal V DD = 1V, V TH = 0.5V, α = 1 All cores can be tested at same voltage. – Optimal V DD same for all cores. 10/25/2015© VLSI Design Conference 201317

18. Optimal V DD for ASIC Z 10/25/2015© VLSI Design Conference 201318 Power constrained test Structure constrained test Optimum V DD 42% reduction in overall test time at optimal V DD.

19. Optimal V DD for ASIC Z 10/25/2015© VLSI Design Conference 201319 Margin between the constraints impacts test time reduction. SC >> PC SC > PC SC = PC SC = Structural Constraint limit PC = Power Constraint limit

20. Next Steps Not all test sessions are power constrained. – Identify and include only power constrained test sessions in ILP. Different cores may be tested at different voltages. – Include voltage range for each core. Optimum VDD for each test session. 10/25/2015© VLSI Design Conference 201320

21. Conclusion Test time minimized by optimizing supply voltage and customizing test clock rate. Proposed method demonstrated on ASIC Z. – 48% improvement over existing solution (300 time units). Main assumption: – Voltage and frequency characteristics of all cores similar. 10/25/2015© VLSI Design Conference 201321