1. Parametric Yield Estimation Considering Leakage Variability Rajeev Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester Present by Fengbo Ren Apr

2. Outline Introduction & Motivation Multiple sources of Variability
Leakage Estimation
Yield Analysis
Summary

3. Leakage Leakage is increasing dramatically with each technology node
Fundamental scaling causes this increase in leakage
Leakage varies super linearly with process variation, temperature and voltage
As we know that, as the technology keep scaling down, the leakage increase dramatically. This picture shows the leakage predicted by ITRS. You can see that first, people think leakage will increase linearly, and then super linearly. This is because that leakage is has inversely exponential relationship with Vth. As we keep scale down the Vth, leakage will increase dramatically.
International Technology Roadmap
IBM, R. Puri, et al, DAC 03
Gate
Sub-Threshold
Leakage has two main components
Sub threshold leakage
Gate Leakage

4. Yield
Number of Parts
Minimum Ship Frequency
Design Spread
Slow
Fast

5. Leakage Variability
This inverse correlation is illustrated. When frequency is high, the leakage varies a lot. Both mean and variance increase significantly. This trend is particularly troubling since it substantially reduces the yield of designs that are both performance and leakage constrained. Hence, there is a need for accurate leakage yield prediction methods that model this dependency.
Observation: Some fast chip consume much larger leakage power
Less L -> less delay -> greatly increase leakage (inverse relationship between delay and leakage)
Decrease yield if we set both performance and leakage as constrains

6. Motivation
Develop a complete stochastic model for leakage current that includes the effects from multiple sources of variability and captures the dependence of the leakage current distribution on operating frequency.
Present an analytical method to quantify the new yield loss when a power limit is also imposed.

7. What is leakage?
Drain
Isub is the drain-to-source current when the channel is turned “off”
For Isub Vg = ‘0’
Igate is the current due to electrons tunneling through the gate-oxide
For Igate Vg = ‘1’
Gate
Source
Isub
Igate
It is estimated that across successive technology generations, sub-threshold leakage increases by about 5X while gate leakage can increase by as much as 30X.

8. What affects Leakage? Input pattern vector (state)
Operating Environment (Temperature, VDD, …)
Gate
Sub-Threshold
How many variables that we need to consider when we talk about the leakage. In this paper, the leakage current is modeled also as a function of these process variations. Which are effective channel length, threshold voltage, and oxide thickness.
Process Variations
(DL, VT, TOX, …)
Topology

9. Leakage and Process Variations
Ileakage = Inominal ⋅ f(ΔP)
where P is the process parameter that affects the leakage current
We further decompose parameter P into two components:
ΔP = ΔPglobal + ΔPlocal
both Δpglobal and ΔPlocal are generally modeled as independent normal random variables making ΔP also a normal random variable.
Global means die to die, which is the variation between different chip on the same wafer, local means within die, which is the variation between different transistors in the same chip. both Δpglobal and ΔPlocal are generally modeled as independent normal random variables making ΔP also a normal random variable.
Since we are only dealing with the deviation from nominal, ΔP is a zero mean variable.

10. Multiple Sources of Variability
Three sources of variability are modeled
Leff, Vt-Doping, Tox
Local and global variations for each
They are treated as independent wrt each other
Chip
Mean
Leff
With-in Chip
Leff Variations
Chip
Mean
Vt-D
Vt-Doping Variations
With-in Chip
Chip
Mean
Tox
With-in Chip
Tox Variations
There are three sources of variability. They are effective channel length, threshold voltage and thickness of oxide. Each of them are decomposed into two part, which are global one and local one.

11. Leakage model basics Total Leakage = Subthreshold + Gate
Subthreshold leakage affected by:
Effective channel length (Leff=L)
Doping (Vth,Nch=V)
Gate leakage affected by:
Oxide thickness (Tox=T)
Process parameters P = {L, V, T} modeled as independent random variables
Empirical models for f(DP)

12. Sub-threshold Leakage Model
Use a polynomial-exponential model
Decompose L, V into global (Lg,Vg) and local (Ll, Vl) components
Previously, leakage had been modeled as a single exponential function of the effective channel length, but as the authors show in a polynomial exponential model is much more accurate in capturing the dependency of leakage on effective channel length. Hence, we use a quadratic exponential model to express f(ΔLeff).

13. Gate leakage model Use exponential model
Decompose T into global (Tg) and local (Tl) components

14. Leakage and with-in chip Leff Variability
Given the large number of transistors on the chip, the total leakage is
The local variability simply reduces to a scaling factor on leakage

15. Leakage & with-in Chip Variability
The local variability is a scaling factor
Just as for Leff, there are scaling factors for Vt and Tox variability

16. Performance and Variations
17 stage ring oscillator, 100nm, for different process cond.
Performance depends on Lg, Vg, Tg
However, strongest correlation is between delay & effective gate length
Author also run another simulation to figure out how this three parameters affect performance. In principle IC or processor frequency depends on all major process parameters, such as gate length, doping concentration, oxide thickness. However, he found from SPICE simulations
that circuit delay is primarily impacted by gate length variations. simulated a 17-stage ring oscillator for different process conditions using the BPTM 100nm process technology as
shown in Figure 2. that circuit delay is primarily impacted by gate length variations. So, in this paper author assume here that frequency will vary with L variation, but given a fixed L, frequency will not vary.

17. Scatter plot of total circuit leakage
Circuit is a large 64-bit adder in 100nm BPTM 7X 3X
Vg, Tg responsible for “local” spread in leakage 3X
Figure 3 gives the scatter plot of the total circuit leakage. The yaxis in the plot has been normalized to the sample mean of the leakage currents. We see that for a 3σ variation in Lg there is a 7X spread in the leakage. Additionally, for a given Lg, there is a wide distribution in the total circuit leakage. For instance, given Lg = 2σ, the normalized value of total circuit leakage is between 0.5 and 1.7. This large distribution is due to the variation in Vg and Tg.
A chip that operates at an acceptable frequency may still have to be discarded because the variability in Vg, Tg pushes its leakage consumption over the tolerable limit. Thus, we see that the secondary variations Vg, Tg play a major role in determining the yield of a lot.

18. Leakage Scatter
we superimpose the sigma contour lines on top of the same leakage scatter plot. For each value of Lg, we calculate (μN,Itot,σN,Itot) and then use Table 1 to construct the contour lines.
Leakage is modeled as a composite lognormal PDF distribution

19. Yield Estimation method
Assume frequency and power constraints (Plim) are imposed
Full chip leakage is a composite lognormal
Performance model is normal
CDF for lognormal (LN) gives yield for specific values of Lg
Lg  Frequency correlation gives yield numbers for each frequency value
 LN
(Isub + Igate)  Dev_type
(Isub + Igate) Full chip
Comp LN
(Ileakage) Full chip
CDF LN
Yield Value  Lg

20. Example yield calculation
Reject (Too slow)
> 27% loss in the faster corner
Reject (Too leaky)
~ 2.5% loss even in the nominal frequency bin
Thus, even if the chip designer budgets for 1.75 times the nominal power, there is a loss of 27.4% of the chips operating in the fast corner. Furthermore, even for the nominal value of Lg=0σ, about 2.5% of the chips are lost since they lie outside the power limit. While a
typical frequency binning method would predict that 100% of the chips with Lg=-2σ are good, our method captures the fact that over 25% cannot be marketed.

21. Yield Table Example

22. Conclusions
Presented a new methodology for statistical leakage current analysis
Closed-form expressions for total leakage current
Considers both inter- and intra-die variation
Multiple sources of variability
New approach to yield estimation considering leakage power variability and its impact on performance

23. Thank you! Questions?