1. 9/01/05ELEC5970-001/6970-001 Lecture 41 ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Low Voltage Low Power Devices Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu

2. 9/01/05ELEC5970-001/6970-001 Lecture 42 Threshold Voltage, V t +-+- 0 < V g < V t + + + + + + + + + + + + + + + + + + Depletion region Polysilicon gate SiO 2 p-type body +-+- V g > V t + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - Depletion region + + + + + + + + + + + + + Polysilicon gate SiO 2 p-type body V t is a function of: Dopant concentration Thickness of oxide

3. 9/01/05ELEC5970-001/6970-001 Lecture 43 Bulk nMOSFET n+ p-type body (bulk) n+ L W SiO 2 Thickness = t ox Gate Source Drain Polysilicon V gs V gd

4. 9/01/05ELEC5970-001/6970-001 Lecture 44 α-Power Law Model V gs > V t and V ds > V dsat = V gs –V t (Saturation region): β I ds =P c ─ (V gs – V t ) α 2 whereβ=μC ox W/L For fully ON transistor, V gs = V ds = V DD : β I dsat =P c ─ (V DD – V t ) α 2 T. Sakurai and A. R. Newton, “Alpha-Power Law MOSFET Model and Its Applications to CMOS Inverter Delay and Other Formulas,” IEEE J. Solid State Circuits, vol. 25, no. 2, pp. 584-594, 1990.

5. 9/01/05ELEC5970-001/6970-001 Lecture 45 α-Power Law Model (Cont.) V gs = 1.8V Shockley α-power law Simulation V ds I ds (μA) 0 0.3 0.6 0.9 1.2 1.5 1.8 400 300 200 100 0 I dsat

6. 9/01/05ELEC5970-001/6970-001 Lecture 46 α-Power Law Model (Cont.) 0V gs < V t,cutoff I ds =I dsat ×V ds /V dsat V ds < V dsat,linear I dsat V ds >V dsat,saturation V dsat =P v (V gs – V t ) α/2

7. 9/01/05ELEC5970-001/6970-001 Lecture 47 α-Power Law Model (Cont.) α = 2, for long channel devices or low V DD α ~ 1, for short channel devices

8. 9/01/05ELEC5970-001/6970-001 Lecture 48 Power and Delay Power=CV DD 2 CV DD 1 1 Inverter delay=──── (─── + ─── ) 4 I dsatn I dsatp KV DD =─────── (V DD – V t ) α

9. 9/01/05ELEC5970-001/6970-001 Lecture 49 Power-Delay Product V DD 3 Power × Delay=constant ×─────── (V DD – V t ) α 0.6V1.8V3.0V V DD Power Delay

10. 9/01/05ELEC5970-001/6970-001 Lecture 410 Optimum Threshold Voltage For minimum power-delay product: 3V t V DD =─── 3 – α For long channel devices, α = 2, V DD = 3V t For very short channel devices, α = 1, V DD = 1.5V t

11. 9/01/05ELEC5970-001/6970-001 Lecture 411 Leakage IGIG IDID I sub I PT I GIDL n+ Ground V DD R

12. 9/01/05ELEC5970-001/6970-001 Lecture 412 Leakage Current Components Subthreshold conduction, I sub Reverse bias pn junction conduction, I D Gate induced drain leakage, I GIDL due to tunneling at the gate-drain overlap Drain source punchthrough, I PT due to short channel and high drain-source voltage Gate tunneling, I G through thin oxide

13. 9/01/05ELEC5970-001/6970-001 Lecture 413 Subthreshold Leakage V gs – V t Isub=I 0 exp( ───── ) nv th 0 0.3 0.6 0.9 1.2 1.5 1.8 V V gs I ds 1mA 100μA 10μA 1μA 100nA 10nA 1nA 100pA 10pA VtVt Subthreshold region Saturation region

14. 9/01/05ELEC5970-001/6970-001 Lecture 414 Normal CMOS Inverter Polysilicon (input) SiO 2 p+ n+ p+ n+ n-well p-substrate (bulk) metal 1 V DD GND output input output VDD GND o

15. 9/01/05ELEC5970-001/6970-001 Lecture 415 Leakage Reduction by Body Bias Polysilicon (input) SiO 2 p+ n+ p+ n+ n-well p-substrate (bulk) metal 1 V DD GND output input output V BBp V DD GND V BBn V BBp o

16. 9/01/05ELEC5970-001/6970-001 Lecture 416 Body Bias, V BBn +-+- 0 < V g < V t + + + + + + + + + + + + + + + + + + Depletion region Polysilicon gate SiO 2 p-type body +-+- V g < 0 - - - - - - - - - + + + + + + + + + + + + + Polysilicon gate SiO 2 p-type body V t is a function of: Dopant concentration Thickness of oxide

17. 9/01/05ELEC5970-001/6970-001 Lecture 417 Further on Body Bias Large body bias can increase gate leakage (I G ) via tunneling through oxide. Body bias is kept less than 0.5V. For V DD = 1.8V: V BBn = -0.4V V BBp = 2.2V

18. 9/01/05ELEC5970-001/6970-001 Lecture 418 Summary Device scaling down reduces supply voltage –Reduced power –Increases delay Optimum power-delay product by scaling down threshold voltage Threshold voltage reduction increases subthreshold leakage power –Use body bias to reduce subthreshold leakage –Body bias may increase gate leakage