1. 2007 MURI Review The Effect of Voltage Fluctuations on the Single Event Transient Response of Deep Submicron Digital Circuits Matthew J. Gadlage 1,2, Ronald D. Schrimpf 1, Balaji Narasimham 1, Bharat L. Bhuva 1, Paul H. Eaton 3, and Joseph M. Benedetto 4 1 Vanderbilt University, Nashville, TN 2 NAVSEA Crane, Crane, IN 3 Microelectronics Research and Development Corporation, Albuquerque, NM 4 Microelectronics Research and Development Corporation, Colorado Springs, CO

2. 2007 MURI Review June 15, 20072 Outline How will voltage fluctuations affect single event transients pulse widths? Data from two unique test chips will be presented Simulations along with a simple model will be used to explain the experimental results [1] Harris, D.; Naffziger, S., "Statistical clock skew modeling with data delay variations," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.9, no.6, pp. 888-898, Dec 2001.

3. 2007 MURI Review June 15, 20073 Motivation [2] Ajami, et. al., "Analysis of IR-drop scaling with implications for deep submicron P/G network designs," Fourth International Symposium on Quality Electronic Design, 2003, pp. 35-40. Voltage drops in advanced CMOS devices are a major concern among circuit designers Mostly due to simple IR drops Expected to become a more significant issue as technologies scale [2]

4. 2007 MURI Review June 15, 20074 Background The probability of a digital single event transient (DSET) causing an upset depends on its width Delay based circuit techniques have been developed to eliminate DSETs Heavy ion induced SET pulse widths in advanced technologies can be as wide as 1 ns Illustration Detailing the Significance of SET Pulse Widths [3] [3] Mavis, D.G., Eaton, P.H., ”Soft error rate mitigation techniques for modern microcircuits,” Reliability Physics Symposium Proceedings, 2002. Pages: 216-225.

5. 2007 MURI Review June 15, 20075 Two DSET Test Chips DICE (Dual Interlocked Cell) Test Chip Consists of a chain of DICE latches with inverters between each latch Immune to static upsets All upsets with this device are due to SETs SET Measurement Test Chip SETs are induced in a large target circuit of inverters To be described in more detail… This device measures the SET pulse width Both devices were fabricated on a 130 nm IBM technology through MOSIS Heavy ion testing was performed at Lawrence Berkeley National Labs

6. 2007 MURI Review June 15, 20076 Two DSET Test Chips DICE (Dual Interlocked Cell) Test Chip Consists of a chain of DICE latches with inverters between each latch Immune to static upsets All upsets with this device are due to SETs SET Measurement Test Chip SETs are induced in a large target circuit of inverters To be described in more detail… This device measures the SET pulse width Both devices were fabricated on a 130 nm IBM technology through MOSIS Heavy ion testing was performed at Lawrence Berkeley National Labs

7. 2007 MURI Review June 15, 20077 DICE Chip Data DICE Chip Data at an LET of 68 MeV-cm 2 /mg 130 nm DICE Chip Schematic Significant increase in cross section from 2V to 1V Average SET width increases with decreasing voltage 1.0 V 1.2 V 1.5 V 2.0 V

8. 2007 MURI Review June 15, 20078 SET Pulse Width Measurement Chip Latch CONTROL SIGNAL n th stage Target Circuit – array of inverters/ NAND/NOR Autonomous or self-triggered SET pulse measurement SET width measured in units of inverter delays Target circuit separate from measurement circuit Trigger signal is actually taken from first stage (shown here as n th stage for clarity) and delayed in time to allow SET pulse to propagate down the measurement circuit stages Target circuit – array of inverters – as they produce long transients with little attenuation

9. 2007 MURI Review June 15, 20079 SET Pulse Width Measurement Data Slight variations in voltage result in a wide variation in SET pulse widths An ~8% decrease in VDD created a ~33% increase in the SET pulse width An increase in SET width will result in a proportional increase in the error cross section in the combinational logic of a circuit SET Pulse Width Measurements vs. Supply Voltage

10. 2007 MURI Review June 15, 200710 SPICE Simulations Input was a constant double exponential current pulse Varied the supply voltage Measured the SET width after 10 inverters ~3X increase in SET width from 2V to 1V A few tenths of volt can change the SET width significantly Strike Here Measure SET Width Here Below Operating Spec.

11. 2007 MURI Review June 15, 200711 Near the SET Threshold… SET threshold is the smallest LET at which a transient will be created An IR drop of only a few mVs can change the threshold value The SET threshold in a modern device may be near that of an alpha particle SPICE Simulation Near the SET Threshold

12. 2007 MURI Review June 15, 200712 MOSFET RC Model Lower VDD => Larger Time Constant => Slower Circuit => Longer Transients MOSFET Resistance Time Constant

13. 2007 MURI Review June 15, 200713 Implications [1] Harris, D.; Naffziger, S., "Statistical clock skew modeling with data delay variations," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.9, no.6, pp. 888-898, Dec 2001. Took an extreme case of IR drop from a microprocessor [1] Plotted the supply voltage variation as a function of die location at a given time The approximate pulse width from the SET measurement chip is shown in each contour region Different locations on a die can have different SET pulse widths (or different error cross sections) 600 ps 800 ps > 1 ns?

14. 2007 MURI Review June 15, 200714 Conclusions Data from two unique test chips were presented to illustrate the effect of voltage fluctuations Small variations in voltage can significantly increase single event transient pulse widths Has the potential to become a more significant issue as devices continue to scale