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Downsizing Semiconductor Device (MOSFET)

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Presentation on theme: "Downsizing Semiconductor Device (MOSFET)"— Presentation transcript:

1 Downsizing Semiconductor Device (MOSFET)
EMT 251

2 Downsizing Device

3 Downsizing Device Downsizing of semiconductor devices (MOSFET/CMOS)
More transistors can be fabricated into single chips. G-Shock Combination Wristwatch (Fujitsu/Flash 0.5 mm pitch by IEP Technologies) MSI (medium) LSI (large) VLSI (very large) ULSI (ultra large scale integration) SCALING DEVICES!!

4 SCALING DEVICE Original Device Scaled Device n+ Volt, V Wiring tox W
Gate Wiring W XD LG n+ tox p-Substrate, Doping = NA Volt, V W/ LG/ tox/ p-Substrate, Doping = NA V/

5 Scaling Technique Scaling of MOSFET device and circuit parameters
Constant-field scaling (Full scaling) Constant-voltage scaling Device dimension (tox, L, W,Xj ) 1/S Power supply voltage (VDD) 1 Electric field (E) S Threshold voltage (VT) Doping density (NA,ND) S2 Drain current (Id) Oxide capacitance (Cox) Capacitance (C) Circuit delay time ( τ ) 1/S2 Power dissipation (P) Power delay (Pτ) 1/S3 Power density (P/A) S3 Sheet resistance (R) Scaling of MOSFET device and circuit parameters

6 STANDARD PARAMETERS PUBLISHED BY ITRS
SIZE LG(µm) TOX(nm) VTH NMOS PMOS 180nm 0.18±15% 4.2±4% 0.40±12.7% -0.42±12.7% 130nm 0.13±15% 3.3±4% 0.34±12.7% -0.35±12.7% 100nm 0.10±15% 2.5±4% 0.26±12.7% -0.30±12.7% 70nm 0.07±15% 1.7±4% 0.20±12.7% -0.22±12.7%

7 Example 150nm 0.15 ±15% SIZE LG(µm) TOX(nm) VTH NMOS PMOS 180nm
0.18±15% 4.2±4% 0.40±12.7% -0.42±12.7% 150nm   0.15 ±15%   ? 130nm 0.13±15% 3.3±4% 0.34±12.7% -0.35±12.7% 100nm 0.10±15% 2.5±4% 0.26±12.7% -0.30±12.7% 70nm 0.07±15% 1.7±4% 0.20±12.7% -0.22±12.7%

8 Example (cont…) VTH NMOS=0.3642 VTH PMOS=

9 Example (cont…) NMOS PMOS Complete CMOS Structure

10 Example (cont…) Id - Vd NMOS PMOS Id - Vg

11 Advantages of MOSFET/CMOS downsizing
High Integration High Speed Operation Decrease the Switching Time of the Transistor Low Cost Low Power Consumption CMOS has the lowest power consumption! Complementary nature of PMOS and NMOS

12 Scaling Limitation Factors
Short channel effect (SCE) Drain-Induce Barrier Lowering (DIBL) Bulk Punch-trough Hot Electron Effect Extra Notes!!

13 THE END


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