XC9500XV The Industry’s First 2.5V ISP CPLDs

XC9500XV Key Features True 2.5V internal operation 75% lower power than 5V CPLDs Complements Virtex FPGA Space-efficient packaging, including chip scale pkg High performance tPD = 3.5ns, fSYS = 225MHz (avail end-1999) 36 to 288 macrocell densities Highest programming reliability 10,000 program/erase cycles Most complete IEEE 1149.1 JTAG support This lists the major, key features of the new 9500XV product family. The key message is the XC9500XV is the INDUSTRY’S FIRST 2.5V ISP CPLD. Initial product strategy should be on the lower power story as well as the space savings afforded by the CSP package offerings. Customers who are either in a pure 2.5V design environment or looking for the lowest power CPLD would be the best candidates for the initial devices, based on a 0.35-micron FLASH process. In late 1999, higher performance with lower power becomes the focus. The device will transition to a 0.25-micron FLASH process which will afford a much faster performing device. Everything else about the XC9500XV family is similar to the XC9500XL, down to the architecture.

XC9500XV Architecture Embraces In-System Changes Advanced, 2nd Generation Pin-Locking Superior routability with speed Maximum Flexibility 54-input function block fan-in 90 p-terms per output 3 global, locally invertible clocks global set/reset pin p-term OE per macrocell clock enable The XC9500XV architecture is identical to the XC9500XL architecture. The XC9500XV and XC9500XL architecture is an enhancement of the popular XC9500 architecture, considered by many to be the most flexible architecture on the market-- for accommodating unexpected in-system changes! Pin-locking continues to improve, with the XL/XV incorporating an even better pin-locking performance. This comes as a result of an enhanced interconnect, more inputs to the function block and significantly enhanced routing software. To make the 9500XLXV family THE most flexible (I.e., best at accommodating design changes while improving speed), we’ve provided this long list of industry leading architecture features. Especially key are the 54 function block inputs. The increase (with the 9500 having 36 inputs) provides more inputs to the function block, better overall utilization and better pin-locking. Only XILINX has 54 function block inputs! 5

XC9500XV System Features Input hysteresis on all pins User programmable grounds Bus hold circuitry for simple bus interface Easy ATE integration for ISP & JTAG fast, concurrent programming times This list itemizes all the great system features that are available on the XC9500XLV as is specifically targeted at meeting the system designer’s needs. Each feature is designed to help the actual application of incorporating a CPLD onto the system board. Again, similar to the XC9500XL list of system features.

New XC9500XV 2.5V Family XC9536XV XC9572XV XC95144XV XC95288XV Macrocells 36 72 144 288 Usable Gates 800 1600 3200 6400 Fastest tPD (ns) 3.5 4 4 5 Highest fSYSTEM 225 200 200 178 Packages (Max. User I/Os) 44PC (34) 64VQ (36) 48CS (36) 44PC (34) 64VQ(52) 100TQ (72) 48CS (38) 100TQ (81) 144TQ (117) 144CS (117) 144TQ (117) 208PQ (168) 256BG (192) The XC9500XV family members mirror the XC9500XL family. Same macrocell range, same I/O numbers, same package offerings. The basic difference is that the XV will eventually offer one faster speed grade than the XL. Note the full complement of pin-compatible package options. Each package has list in parenthesis the actual number of I/Os. Easy density migration is available for all like packages. This lowers the users risk when his/her design grows. The XC95144XV in the TQ100 will be the first member available, with engineering samples available as of end-Jan. The other members will be available as engineering samples throughout Q2. Initial speed grades will be -10C for the XC9536/72/144XV and the -15C for the XC95288XV. BGA CSP 9

Most Complete JTAG Testability IEEE Std 1149.1 boundary-scan testability & advanced system debug/diagnosis 8 instructions supported (incl. CLAMP) Full support on all family members Industry-standard ISP interface Complete 3rd party support The XC9500XLV family has the most complete, industry-standard JTAG boundary-scan capabilities -- supporting an important capability for all new system designs. In addition to manufacturing test benefits, JTAG boundary-scan enhances development and debug as well, especially in complex, tightly packed systems. JTAG allows all internal nodes to be read out using only the 4 JTAG pins! The XC9500XV (along with XC9500 and XC9500XL) is the only CPLD family to support full JTAG boundary-scan in the whole CPLD family -- even lower density devices! The JTAG-based in-system programming (ISP) protocol allows compliance with emerging standards, such as the IEEE 1149.1 subcommittee formalizing a standard for ISP. 6

Chip Scale Packaging Leadership Supports high-growth market segments: Communications, Computers, Consumer New 48-pin CSP: 1/3 size of the VQ44 Xilinx has lead the industry again with the introduction of the small, space-efficient Chip Scale Package. The CSP solution is available on the 36XV/72XV and 144XV. The smaller package makes it ideal for applications that require programmable logic in the smallest footprint possible. Uses standard IR techniques for mounting to PC board

XC9500XV Offers Lower Power 5v Core Voltage 1.0 .75 Power (normalized) 75% less power! .5 3.3v 2.5v .25 The XC9500XV’s lower power is one of the highlights of the product family. By offering 75% less power consumption than a typical 5V CPLD, it opens up many designs that couldn’t use Xilinx CPLDs because of power constraints. The superiority of Xilinx’ FastFLASH is the key to moving to lower power in record time. XC9500 XC9500XL XC9500XV * Same frequency and typical utilization

Quick Technology Upgrade Initial Production -10/-15 Speed Grades 2.5V Vccint w/ 2.5V Vccio Commercial Temp Range 0.25m 5LM FLASH Performance Technology Upgrade High-Performance Devices up to 3.5ns, 225 MHz 2.5V Vccint w/ 3.3 Vccio Commercial & Industrial Temp Ranges 0.35m 4LM FLASH The XC9500XV will be introduced in a 2-phase schedule. The initial devices released in phase I will be based upon the 0.35-micron FLASH process. This means that devices will be of the slower speeds and capable of only driving 2.5V outputs (3.3V I/O tolerant, however). In phase II, in late 1999, the family will transition over to the 0.25-micron FLASH process. This will enable the high performance devices to be available. Specifically, 3.5ns in the XC9536XV, 4ns in the XC9572/144XV and 5ns in the XC95288XV. The rapid move to the new process technology will mean lower cost, but customer will not need to wait to get lower pricing. From introduction, the XC9500XV is priced to be lower than the XC9500XL, up to 20% lower! The XC9536/72XV are 5% lower than the XC9536/72XL; the XC95144XV is 10% lower than the XC95144XL; and the XC95288XV is 20% lower than the XC95288XL. Phase I Phase II Up to 20% Lower Price Than XC9500XL

Xilinx CPLD Process Leadership Non-Volatile Year used in Year used in SPLD/CPLD Technology Memories SPLD/CPLD Pioneer Bipolar Fuse 1973 1978 MMI (AMD) EPROM 1979 1984 Altera EP-series 5V EEPROM 1986 1991 Lattice ispLSI XC9000 Series Xilinx is always committed to providing leading edge programmable logic solutions by adopting the latest technologies. The XC9500/XL/XV are based upon the most dominant technology available: FLASH. With the introduction of the XC9500XV family, Xilinx now offers a full suite of voltage options: 5V, 3.3V, and 2.5V. All three families combine to make up the XC9000 Series of CPLDs. 5V FLASH 1990 1995 Xilinx XC9500 3.3V FLASH 1993 1998 Xilinx XC9500XL 2.5V FLASH 1995 1999 Xilinx XC9500XV

Productive Implementation Flow for CPLDs Simplified Project Management Implementation Templates for Speed & Density Push Button Design Flows USER BENEFITS Faster Clock Speeds Higher Device Utilization optimized logic/cm2 Industry’s Best Pin-Locking more design flexibility, less risk, lower cost The new v1.5 software provides CPLD designers with one of the industry best design flows available today. From the simple project manager, to the ready-built speed and density templates, and the push-button design flow manager, Xilinx CPLD software provides the designer with an excellent solution. These enhancement apply to both Foundation and Alliance software solutions from Xilinx.

Xilinx Lowering Cost Across The Supply Chain LEADING EDGE TECHNOLOGY STREAM-LINED OPERATIONS “MEMORY STYLE” MANUFACTURING 1st with Flash ISP Only true 0.35um Apply memory R&D advantages to CPLDs Long-term foundry agreements Stream-lined device/pkg offerings High volume packages 10ns slowest speed grade Off-shore sort, test and assembly Multi-site parallel test Fast time-to-market Xilinx has a very aggressive supply chain management program aimed at reducing cost, providing high volumes of product, in the right product options. Our Flash technology benefits are numerous and proven out by all the major memory vendors today. Operations are streamlined for efficiency and our manufacturing flow is set up very much like the way memories are handled today. All this supports our strategy of providing the most cost efficient CPLD in the industry. 9

The XC9000 Series The Complete CPLD Solution Product Life Cycle Support Complete Voltage Offering to Meet Every Design Need 5V, 3.3V, 2.5V Leadership Features Productive Software Lowest Cost Solution Xilinx has taken the lead in CPLDs by being the first to offer a complete series of CPLDs to meet every design need. Each of the families in the XC9000 Series offer superior architecture, advanced features and the lowest cost. Implementation from design to manufacturing to field upgrades is easy with Xilinx XC9000 Series of CPLDs.