Hellenic Open University Physics Laboratory School of Science and Technology Hellenic Open University George Bourlis PMT Readout and Floor Triggering Charge estimation using the times over the thresholds Event Building and Triggering + multiplicity 20 3” buizen -> 40 PMTs polystyrene In the framework of the KM3NeT Design Study

ReadOut Electronics 5 PMT Signal Inputs Trigger Output USB Port HPTDC 32 channels (LR) – 8 Channels (HR) 25ps (HR) to 100 ps (LR) accuracy Self Calibrating 25ps accuracy TDC GPS Input

Time (ns) Trigger Input

Gain vs HV Calibration @ “nominal” H.V. gain: ~ 4 105 <charge>/p.e. ~ 0.07pCb <pulse height>/p.e. ~ 1.05mV Rise Time: 1.2 ns The Photomultiplier Tube: PH: XP1912 Charge (in units of mean p.e. charge) At the Detector Center Data - Monte Carlo Prediction Charge (pCb) Single p.e Gain vs HV Calibration

Charge versus Time Over Threshold Charge (pC) Time Over Threshold (s) 1st Threshold only 1st & 2nd Threshold 1st, 2nd & 3rd Threshold 50mV 15mV 4mV

Charge Parameterization 1st & 2nd Threshold 1st, 2nd & 3rd Threshold

Charge Estimation - Estimated Resolution ~10% 1st & 2nd Threshold 11% 1st, 2nd & 3rd Threshold 8% - Estimated Resolution ~10% - Better if all thresholds are crossed

Charge Estimation - σ=(1.01 ± 0.01) (2 thresholds) 1st & 2nd Threshold 1st, 2nd & 3rd Threshold - σ=(1.01 ± 0.01) (2 thresholds) - σ=(1.1 ± 0.1) (3 thresholds)

HPTDC architecture HPTDC is fed by a 40 MHz clock giving us a basic 25 ns period (coarse count). A PLL (Phase Locked Loop) device inside the chip does clock multiplication by a factor 8 (3 bits) to 320 MHz (3.125 ns period) . A DLL (Delay Locked Loop) done by 32 cells fed by the PLL clock acts a 5 bits hit register for each PLL clock (98 ps width LSB = 3.125 ns/32). 4 R-C delay lines divides each DLL bin in 4 parts (R-C interpolation) in high resolution (25ps) mode.

Trigger Matching Logic