MR (7/7/05) Trip chip ref.: McFarland_MINERvA_Electronics.pdf (presentation at Rome T2K meeting, 6/12/04) discusses possible use of Trip (not Trip-t) ASIC in T2K Trip-t is newer version of Trip (we would be more likely to use Trip-t but this talk still has some interesting info) - generally positive, and gives estimates for front end costs ~ $440k for 30k channel system + $100k LV distribution + $100k DAQ Trip ASIC (32 channels – packaged chip) integrate charge over spill (or bucket), variable preamp gain up to 4 pC dynamic range 48 stage pipeline stores analogue samples fast discriminator output -> FPGA -> timing in 5 nsec steps (could possibly do better) FPGA then passes pipeline trigger back to Trip 32 analogue samples muxed out to commercial ADC (12-bit)
MR (7/7/05) Trip -t chip ref.: TRIP_t_Apr05.ppt (Bellantoni – D0 AFEII Director’s Review, 13/4/05) summarises measured performance of Trip-t & spec. improvements for 2 nd version (in fab now I think) Trip-t ASIC (32 channels - packaged) integrate charge over spill (or bucket), variable preamp gain up to 3 pC dynamic range 48 stage pipeline stores analogue samples –> A pulse (7 bit precision) noise < 1 fC (not sure whether this gain range dependent) time between disc. firing (any channel) and end of integration period -> t pulse (~ 2nsec res’n) t pulse also stored in 48 stage pipeline disc. outputs read out during reset period -> FPGA -> pipeline trigger to Trip-t 32 A samples and 32 t samples muxed out to commercial ADCs power < 10 mW/channel Is above spec. adequate for T2K application?
possible new FE chip architecture thresh pk.hold fast preamp slow amp SiPM disc. pk.hold SiPM pk.hold SiPM ADC HV trim control combine disc. O/Ps and generate address of channel that fired e.g. 16 channels 4 bit add. n bits control fast timing signal front end chip ~ 20 lines front end digital (FPGA based) functionality fast time stamp (~ns) control digitization of channel that fired assemble data packet and transmit (channel address, time stamp, ADC value) slow control set up HV trim, channel gains, thresholds, … would expect one FE FPGA to deal with more than one FE chip (maybe 8?) nothing “particularly” difficult here fast time stamping performed off-chip
MR (7/7/05) Idea to keep very fast functionality off FPGA good idea from Matt Noy fast discriminator O/P from FE chip deserializer chip e.g. DS90CR486 FE FPGA 133 MHz only 800 MHz PLL whichever line shows discriminator output first -> timing at 1/6 th of 133MHz period (1.25 nsec.) DS90CR486 -> 8 channels of 1:6 deserialization (8:48) => 1 chip for 8 FE chips 900 mW power => 7 mW / FE channel
MR (7/7/05) Chip count 16 channel FE chip 16 SiPMs FE FPGA 16 channel FE chip 16 SiPMs 16 channel FE chip 16 SiPMs 16 channel FE chip 16 SiPMs 16 channel FE chip 16 SiPMs 16 channel FE chip 16 SiPMs 16 channel FE chip 16 SiPMs 16 channel FE chip 16 SiPMs 50,000 channels 50,000 SiPMs 3125 FE chips (assume 16 channels) (maybe 390 deserializers) 390 FE FPGAs FE FPGA FE FPGA FE FPGA FE FPGA 390 readout lines off-detector (or could combine)
MR (7/7/05) Trip-t chip / new chip – a few pros and cons Trip-t chip Pros No FE chip development required no development cost – just buy chips May be able to utilise other parts of Trip-t readout system? (or at least follow same approach) Trip-t chip Cons possible signal size incompatibility few pC, we need few 100 pC unless lower gain on SiPM (maybe could just attenuate?) no HV trim (may be possible to provide with commercial components) time resolution performance not good (but should be better for next version) more complicated functionality than necessary for T2K (e.g. pipeline) New chip Pros FE specification and functionality can be tailored to SiPM everything under our control New chip Cons development cost risk