1. 1 TOF Electronics Overview J. Schambach University of Texas DoE Review, BNL, 25 Sep 2006

2. 2 Outline Electronics “Essential Model” Trigger & DAQ Interfaces Board Status Production & Testing

3. 3 TOF Electronics Top Level

4. 4 Electronics for One Side

5. 5 Tray Level Electronics

6. 6 Front-End Electronics “TINO” 8 per tray 960 total

7. 7 CERN/LAA NINO Chip developed for ALICE ParameterValue Peaking time1ns Signal Range100fC – 2pC Noise (with detector)< 5000 e- rms Front edge time jitter<25ps rms Power consumption30 mW/ch Discriminator threshold10fC to 100fC Differential Input impedance40Ω< Zin < 75Ω Output interfaceLVDS

8. 8 Digitizer Board “TDIG” 8 per tray 3 per start side 966 total

9. 9 INL Correction Sigma = 0.9 timebins = 22 ps Implies single channel resolution of 16ps

10. 10 Tray Controller “TCPU” 1 per tray 1 per Start Detector 122 total

11. 11 DAQ/Trigger Interface “THUB” 2 per Detector side 4 total

12. 12 THUB Design

13. 13 ALICE DDL Link Front-end electronics Detector Data Link DDL SIU DDL DIU RORC Source Interface Unit Destination Interface Unit Read Out Receiver Card PC Data Acquisition PC Optical Fibre ~200 meters

14. 14 PMT Input Board “TPMD” 3 per Start Detector 6 total

15. 15 Interface to L0 trigger Provides multiplicity at 9.4 MHz with <~700 ns latency. The multiplicity range is 0-24 for each tray, where one is added to the sum if any of the 8 TOF channels in a NINO chip is above threshold. TDIG receives the multiplicity information from the NINO and passes it to TCPU. Each TCPU will send the multiplicity over 5 pairs to the Level 0 DSMI on the south platform. These cables all need to be the same length (+- 1 ns). Each DSMI can handle 128 bits of input. We plan to use 100 bits on each DSMI, representing 20 trays. Each DSMI has 8, 32-pin connectors. 6, 32-pin connectors will each serve 3 trays, 1 connector will serve 2 trays, and 1 will be unused. We plan to time in the signal to trigger by trial and error. We plan to scan the trigger info in ~10 ns steps using various cable lengths to find the sweet spot. The logic pulse should be >30 ns. Initially (this year), we will “self-latch” the data. Each TDIG will send a value between 0 and 3 to TCPU, TCPU sums the data and sends it to the DSMI If “self-latching” doesn’t work, we are considering modifying the DSMI to send the RHIC strobe to each tray’s TDIGs, learn the phase of this clock at each TDIG, and use it to latch the data on each TDIG

16. 16 Interface to Level-2 Trigger Interface is the identical DDL link that will be used to connect TOF to DAQ. Initially, it was planned to provide a 23k bit map of the TOF hits to L2 for each L0 trigger, 192 bits per tray, where each bit represents a hit channel. In principle, same (timing) data presented to DAQ can also be provided to L2, needs just a change in firmware Data volume is big: –Fully occupied TOF: 385,888 bits per event per THUB –Assuming <20% occupancy: 77,178 bits per event per THUB –10kHz L0 rate: 736 Mbits/sec per fiber ~ 92MBytes/sec per fiber –Total for 4THUBs: 2944 Mbits/sec ~ 368 MBytes/sec, four fibers Data is uncorrected, needs INL correction (lookup table?) and slewing correction

17. 17 Interface to DAQ The TOF system needs to be faster than the upgraded TPC so as not to introduce any additional dead time. The TOF information is only useful in a STAR event if the TPC is also readout in that event (for tracking). The system is able to handle L0 accept commands at >10 kHz. The system will not process L2-accept or Abort commands, but rather pass those on to DAQ (as separate events) over the fiber for DAQ to process. The current system design foresees sending all events to DAQ independent of any higher level trigger decisions for each Level-0 trigger. This design does not require much memory on THUB other than a small amount (arranged as a FIFO) to decouple the clock domain on the TCPU (SERDES) side from the clock domain of the SIU interface.

18. 18 DAQ Data Rates

19. 19 Current System Status

20. 20 TINO Status Motivation: Replace Maxim Amplifier & Comparator of TAMP with custom ASIC “NINO” incorporating both functions: –Lower Cost –Power (no negative supply & lower power, fewer power supplies) –Fully differential: better match to HPTDC –Pulse stretching: one TDC can measure both leading & trailing edge Decision to use TINO instead of TAMP was reached in Feb 2006 based on cosmic ray testing (see following slides) with both TAMP and TINO giving similar timing resolutions Automated TINO prototype production has been achieved, fabricated 35 circuit boards, 15 out of 15 boards successfully assembled Minor revisions made to design and layout for part availability and assembly reasons Mechanical compatibility with tray design verified Will install & test 8 TINO on tray in Run 7

21. 21 UT Cosmic Ray Test Setup Readout through TAMP/TINO, TDIG, and TCPU dT = t3 – (t1+t2+t4)/3 Same INL correction for all HPTDCs S1 S2 S3 Gasbox MRPC 1 MRPC 2 MRPC 3 MRPC 4 3.00 2.00 22.00 8.50

22. 22 UT Cosmic Ray Test Results Time-over-Threshold (ToT) Slewing Corrections Final Timing Resolutions average σ(delta t) ≈ 91ps TAMPTINO

23. 23 TINO Test Plan NINO chips were fully tested @ CERN after packaging Confirm timing & crosstalk performance of TINO design in TDIG RFI environment Verify input to output integrity of each PCB assembly Verify PCB assembly, current drain Measure, with TDIG readout, for each channel: –Threshold input voltage required to produce “0” discrimination threshold –Overall gain, (input discrimination level @ max. threshold) –Output pulse width “stretch”

24. 24 TINO Test Items Needed Power supply with accurate current metering Pulser with –MRPC input attenuator / shaping / connector jig –PC interface (for automated testing) Production TDIG PC with readout / control software to implement desired degree of test automation

25. 25 TPMD (start side FEE) New replacement for “TPMT” to match start detector electronics to tray electronics Design considerations: –Map 4 channels max. per HPTDC to minimize crosstalk effect –Outputs provided for (“fast”) Z-vertex FEE (not part of the TOF project) Status: –Design and layout completed –Printed Circuit Boards and parts ordered

26. 26 THUB Status Needed to concentrate data before sending to DAQ in order to reduce the number of DAQ-fiber interfaces Also provides interface to Level-2 Prototype designed @ UT, first board delivered in April 2006 with 4 SERDES links assembled TCPU-THUB interfaces implemented as SERDES on daughter cards; distributes trigger, clock, and resets to TCPU, receives data from TCPU SERDES link works reliably up to ~25 feet @ 40MHz, > 50 feet @ 20 MHz. Need about 30 feet for start detector cable run A cable delay test performed with a TCPU clock driven by a SERDES derived clock and a Run 5 TDIG shows no difference in timing resolution. This indicates derived clock has small enough jitter to operate HPTDC reliably. Probably use 20MHz on SERDES link, multiply to 40MHz on TCPU. Will try to add buffer to see if cable length at 40MHz can be increased.

27. 27 THUB Plans Need another revision for final THUB –Add Level-2 interface (SIU) –Correct minor issues with prototype –Possibly place SERDES on main board (no daughter cards)? Need about 3 weeks of circuit design work and about 4 weeks for layout of final revision Production and assembly takes about 4 weeks (only 4 boards are needed) Board locations on the STAR magnet have been documented within STAR Cable runs were discussed with R.Brown Two prototype THUB (one for East and one for West side) will be ready Nov 2006 for installation in Run 7. Final revision of THUB is not needed until Run 8. Final design review will depend on TCPU design, probably combined with TCPU Final Design Review

28. 28 TDIG & TCPU Status New design for TDIG almost completed Plan to build 4 to confirm functionality, then order about 20 for Run 7 and bench testing TCPU design will start as soon as TDIG design is finished Details presented in Lloyds talk See also Geary Eppley’s talk regarding the Blue- Sky contract for these boards

29. 29 Production & Testing

30. 30 Schedule TDIG Design close to being finished, prototype production to start soon. TINO design finished and first 15 boards produced and assembled. Final production can start as soon as compatibility with new TDIG has been bench tested TCPU R&D should be finished by Jan 07 TPMD design finished and production of 15 cards has started. Delivery expected in 5 weeks. THUB design should be ready for final design review in Jan 07. Plan for a system test with all electronics components Final Design review shortly after first TCPU prototypes have been bench tested (Jan 2007)

31. 31 Production TDIG production rate: ~100 boards per month. Total production should start in Dec 06 and be finished in less than 18 months (~Apr 2008) TINO production will stay ahead of TDIG production at about the same rate TCPU production will be in parallel to TDIG production, but need fewer boards TPMD production can be finished with one order THUB production can be finished in one order

32. 32 Electronics Testing Bare board testing and simple stuffed board testing at Vendor Simple single board functionality testing Test board set of 8 TINO, 8 TDIG, and TCPU (all tray electronics) as a set on a real tray top Test installed electronics on a tray in a cosmic ray setup

33. 33 Electronics Test Plans

34. 34 Additional Slides

35. 35 HPTDC Time Measurement Coarse time (bin width 25 ns, 11 bits) PLL bits (bin width 3.125 ns) DLL bits (bin width 98 ps) MSB LSB R-C bits (bin width 24.4 ps) HPTDC is fed by a 40 MHz clock giving us a basic 25 ns period (coarse count). A PLL (Phase Locked Loop) device inside the chip does clock multiplication by a factor 8 (3 bits) to 320 MHz (3.125 ns period). A DLL (Delay Locked Loop) done by 32 cells fed by the PLL clock acts as a 5 bit hit register for each PLL clock (98 ps width LSB = 3.125 ns/32). 4 R-C delay lines divide each DLL bin in 4 parts (R-C interpolation)

36. 36 HPTDC Buffering & Readout Level-0 Trigger Bunch Crossing Hit Buffer Level-0 Buffering 8 channel @ 25ps or 32 channels @ 100ps

37. 37 Crosstalk measurements Noise signal START Signal STOP Signal ss HPTDC 1 Ch. 1-7 Ch. 0 HPTDC 2 Ch. 23 T start -T stop Cross Talk check: Analyzing shifts of T start -T stop while varying  s

38. 38 ALICE & CAEN Cross Talk Stop – Start Measurement Start = Channel 0, Stop = Channel 7 Disturbing Channel on Channel 1 Stop disturbed Start disturbed

39. 39 Crosstalk Results Disturbing Signal On Channel: Ch 1Ch 2Ch 3Ch 4 Ch 5Ch 6Ch 7Ch 12 -10ns Ch 1 – Ch 7 = Same chip Different chip

40. 40 Crosstalk in Run 5 Data 1 hit 3 hits all 2 hits

41. 41 UT Cosmic Ray Test Results INL corrected time differences Time-over-Threshold (ToT) Distributions (TAMP) Slewing Corrections Final Timing Resolutions σ(1 channel) = σ / √(3/2) → average σ ≈ 91ps

42. 42 Electronics Installation

43. 43 Electronics Items To Install THUB: –4 boxes, 2 on each magnet face, about 30inx15inx10in, 180 degrees apart from each other –Box design and exact location still need to be determined –Installation by STSG THUB-TCPU Interconnects: –120 CAT5/6 cables –Installation by TOF CANbus cables: –4 cables from South platform to 4 THUB cards –4 cables from THUB to trays –120 cables from tray to tray –Installation by TOF/STSG Fibers: –4 dual fibers from THUB to DAQ –4 fibers to Trigger-L2 boxes

44. 44 Electronics Items to Install (continued) Low Voltage Supplies: –12 Wiener Mainframes in 2 racks –Installation by STSG Low Voltage cables: –2 voltages plus 2 sense wires per tray, already attached to tray at time of installation; 120 wire assemblies total –Cut to correct length and terminated at time of installation –Installation by STSG TCD cables: –4 cable assemblies from TCD distribution crate to 4 THUBs –Installation by TOF? Multiplicity cables: –120 ribbon cables from trays to trigger DSMs –Installation by Trigger

45. 45 Run 5/6 Setup

46. 46 Run 5/6 Setup

47. 47 Run 5/6 Setup

48. 48 Run 5/6 Setup

49. 49 Run 5/6 Setup

50. 50 Board Status BoardCurrent Status Future Plans Timeline TPMTUsed in Runs 5 & 6Rev design: add discriminators Ready for production by Q4 FY06 TINOPrototype designed and built. Testing with cosmics ongoing Test in test beamDecision milestone by Q2 FY06, Production by Q4, FY06 TDIGUsed in Runs 5 & 6Rev design by Q3 FY06: delete comparators & 1 TDC, add L0-mult., L2 Production by Q4 FY06 TCPUPrototype with additional features used in Runs 5 & 6 Add TCPU-THUB I/F, delete SIU, TCD I/Fs Production by Q4 FY06 THUBPrototype currently in preliminary design stage Prototype with 3 I/F channels, redesign after bench test Production Q1 FY07