1. QUARTIC TDC Development at Univ. of Alberta
Jim Pinfold, Shengli Liu,
Bill Burris, John Scaapman
University of Alberta,
December 2, 2008

2. Features: 8 Channel TDC Board Prototype
Targeting at below 20 ps RMS resolution;
(STAR TOF reported 24 ps, ALICE TOF reported 20 ps, Ref: 1,2)
8 differential LVPECL input channels ;
1 HPTDC (v1.3) chip from CERN in Very High Resolution Mode;
Altera Cyclone2 FPGA, Cypress USB chip for local debug;
Serial LVDS link to connect to the main RODs;
Both USB and the Serial LVDS link provide the timing and control signals to HPTDC;
Ref 1: J. Schambach, “Proposed STAR time of flight readout electronics and DAQ”, Computing in High Energy and Nuclear Physics, 24-28, March 2003, La Jolla, California.
Ref 2: P. Antonioli, “A 20 ps TDC readout module for the ALICE time of flight system: design and test results”. 9th Workshop on Electronics for LHC Experiments, Amsterdam, The Netherlands, 29 Sep - 3 Oct 2003, pp

3. Development history: 8 Channel TDC Board Prototype
January to April 2008: Development of Schematics and PCB, FPGA coding/Simulation;
May: PCB assembly;
May to June: FPGA coding, TDC Programming and DLL, RC Parameter adjusting;
June to August: Performance testing at University of Alberta.

4. 8 Channel TDC Board Prototype

5. 2 boards and NIM-PECL, TTL-PECL translators

6. Testing setup Code Density Test for DNL, INL:
Quartic TDC
Pulse
Generator
To PECL
Cable Delay Test for RMS resolution:
To PECL
Pulse
splitter
Quartic TDC
Pulse
Generator
Extra Cable Delay
To PECL
Code Density Test is the common way to test the nonlinearity of TDC. The basic idea is to feed the TDC with
a large number of randomly distributed pulses, so that an ideal TDC should give a flat histogram plot for DNL (Differential
Nonlinearity). Otherwise this histogram is the DNL, and the integration of the plot is the INL.
Cable Delay Test is to measure the RMS resolution:
The pulse splitter is a passive component and the jitter introduced by PECL adaptor is minimum, the two pulses arrive at TDC have
Almost fixed delay relationship.
Differential Nonlinearity
Integral Nonlinearity

7. TDC’s RMS resolution
For the Cable delay test, the delay is measured by TDC, and has a statistical distribution. The RMS of the distribution is defined as the RMS resolution.
Single channel RMS resolution is defined by RMS resolution divided by square root of 2.
On this plot, the bin size is 25 ps, the single channel rms resolution is 12.2 ps.
The delay value between two signals plotted as histogram;
RMS resolution = RMS of the delay value distribution;
Single Channel RMS resolution = RMS resolution / sqrt(2);

8. HPTDC: DLL and R-C delay line
DLL has 32 delay elements to divide the main clock as shown in the diagram, this gives bin size of 100 ps at the Very High Resolution Mode;
R-C delay line has 4 delay elements, to further divide 100 ps, to finally get 25 ps bin size.
Courtesy from J. Christiansen, “HPTDC Manual”

9. HPTDC: data bits combination
DLL gives 5 bit Fine[4:0],
R-C Delay Line gives the LSB 2 bit Interpolation[1:0].
Courtesy from J. Christiansen, “HPTDC Manual”

10. Testing results: DNL
That pattern shown is the remaining DNL of the DLL (Delay Locked Loop) after the DLL taps are compensated by HPTDC manual recommended values.
The pattern period is 128 bin, 3.2 ns, which is the delay length of the DLL structure in the HPTDC.

11. Testing results: INL
We could see the maximum INL is within 8 LSB, that is to say no more than 4 bit LSB.
And since the granularity of the INL data is better than 4 bit, so we could use more bits to do the correction, for example 8 bit.

12. Testing results: Summary for DNL and INL
All channels have the similar DNL patterns, values.
INL has very small changes on different channels. But still different INL compensation on each channel makes difference on resolution results.
4 bit is enough for standard INL compensation.
Standard means without expanding data bit width.

13. Testing results: RMS resolution without INL correction

14. Testing results: RMS resolution with INL correction

15. Testing results: RMS resolution with INL correction
With 8 bit correction, the bin size becomes 25 ps/ (2**4) = ps.

16. Testing results: RMS resolution vs. delay
This is the resolution when different delay is applied to the two measured channels.
Shown is with 4 bit INL correction, single channel RMS resolution is between 12 to 13.6 ps.

17. Testing results: RMS resolution for channel 0 to other channels
This is the RMS resolution measured for different channels.
Shown is with 8 bit INL correction, single channel RMS resolution is between 9.6 to 11.4 ps.

18. Summary 2 TDC boards have been built and tested, each with 8 input
VHRM (Very High Resolution Mode: 25 ps bin size) with USB interface and LVDS link to downstream Read out.
RMS resolution is smaller than 15 ps for both boards with 4 bit INL compensation.
RMS resolution is smaller than 12 ps for both boards with 8 bit INL compensation.
RMS resolution performance does not change very much among different channels, and not very much either for different delay time in the range of 25 ns. (periodically with 25 ns)
This is the resolution when different delay is applied to the two measured channels.
Shown is with 4 bit INL correction, single channel RMS resolution is between 12 to 13.6 ps.