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Low Cost TDC Using FPGA Logic Cell Delay Jinyuan Wu, Z. Shi For CKM Collaboration Jan. 2003.

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Presentation on theme: "Low Cost TDC Using FPGA Logic Cell Delay Jinyuan Wu, Z. Shi For CKM Collaboration Jan. 2003."— Presentation transcript:


2 Low Cost TDC Using FPGA Logic Cell Delay Jinyuan Wu, Z. Shi For CKM Collaboration Jan. 2003

3 Introduction PMT hit Q ADC/ QIE FPGA COM PORT TDC Need TDC Low cost FPGA

4 Low Cost FPGA Companies maintain low cost product lines. –Altera: ACEX 1K ($11.50 -- $31.50). –Xilinx: Spartan-IIE ($17.50 -- $26.50). The low cost devices have enough logic cells and RAM for data packing, etc. TDC can be implemented using internal chain structure. (This is not as good as DESER, but is available today). Use digital method to do compensation.

5 TDC Using FPGA Logic Chain Delay This scheme uses current FPGA technology Low cost chip family can be used. (e.g. EP1K10QC208-2 $15.25) Chain structure exists in Altera ACEX, Xilinx Spartan families. IN CLK

6 Problem 1: Logic Cell Delay Time Difference Delay times in different logic paths are different. The FPGA compiler is not easy to control. -- The logic path is not easy to predict. Solution: use chain structure in the FPGA. There are many type of chain structures: cascade chain, carry chain, sum of product chain, BY – YB chain, etc.

7 Problem 2: Delay Time Change With Temperature Delay time changes with temperature and power supply voltage. In DESER or TMC, the delay time of the delay chain is compensated by adjusting relevant voltages. – Analog compensation. In FPGA, digital compensation is needed. Digital compensation uses delay speed measured in the same delay chain to correct the arrival time of a hit.

8 Delay Chain Digital Compensation IN CLK Cell delay is not easy to adjust with analog methods. Digital compensation is needed: –Use longer delay line. –Some signals may be registered twice. N 2 -N 1 =(1/f)/  t The two measurements can be used: –to calibrate the delay. –to reduce digitization errors.

9 A Test Implementation Chip: Altera ACEX, EP1K10QC208-1 ($22.50) on the COMADC board. Clock: 35 MHz external (to fit QIE test readout), 70 MHz inside the chip. Digitization error: 0.4 ns/LSB, (too good. The chip is too fast). Jitter: < 1 LSB.

10 The Board and the Chip

11 The Core Part of the Chip Delay Chain Altera “cascade” chain Register Array

12 Compiled Resource Map Delay Chain and Register Array (48 Steps)

13 Logic Analyzer Output (1) Input Hit Pattern in Delay Chain TDC OK TDC Value

14 Logic Analyzer Output (2) Different Input Time Different Hit Pattern TDC OK Different TDC Value

15 Logic Analyzer Output (3) Some Signals … … can be seen 2 times…… generating 2 TDC values.

16 Test Results: Raw Data Power supply voltage changed to create variation of the delay. V = 2.5 to 1.8V: the change is very big. 30% cell delay variation is seen. 2 nd TDC 1 st TDC

17 Effect of Digital Compensation Without compensation, 2.5ns error is seen. With compensations, error reduced to <1ns.

18 Two Compensation Methods Method 1: (tao) allows divisions. It is suitable for offline compensation. Method 2: (tao3) uses Taylor expansion to avoid divisions. It is suitable for FPGA hardware. 0.5 ns

19 To Do Use slower chip: EP1K10QC208-2 ($15.25) to repeat the study. Implement hardware compensation algorithm in the chip. Hook up to QIE test readout system to study random signal performance. Documentation.

20 The End Thanks

21 TDC Solutions ASIC: good for large total system channel count. FPGA with DESER: good for large channel count per package. (CYP15G04K100V1MGC $285.) Other situations? Consider low cost FPGA. Tot sys ch. Ch/pkg

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