1. R&D for single gap -Use the HARDROC ASICs, SiGe technology (well tested and available) HARDROC : 64-channel, 2-bin readout (3 comparators, 3 thresholds), Dynamic range : 10fC-10pC - Use SDHCAL DAQ (available) - Use a TDC with 100 ps time resolution (available) per ASIC (use the OR64 available signal for each of the three comparators as input) - Design new PCB with pick-up strips (pitch of 2.5 mm) on the two faces of the PCB with 1 mm staggering between the two faces. ASICs are embedded on the PCB. 4.7 mm 4.3mm

2. OR64 Charge DIF #2 Time DIF #2 Time DIF #1 Charge DIF #1 DAQ soft T = N 0 T slow - N 1 T fast

3. Charge DIF TDC DIF HR2 (top left strips) HR2 (bottom left strips) HR2 (top right strips) HR2 (bottom right strips)

4. Preliminary results (1) Injection is made with a pulse generator on one strip (other channels are disabled) Pulse generator is triggered by the DIF (synchronous with the DIF clock) Delay between pulse and trigger is adjusted inside the generator Pulse generator (HP33250) SDCCDCCQ DIF T DIF ASU PCRPi USB Trigger HR2

5. Preliminary results (2) 6mm from start of strip (run 13411) 30 mm from start of strip (run 13424)  around 2,6 ns/m on the PCB even if obviously not linear Can certainly be refined but not too far from curently accepted values

6. R&D for multi gap and <100 ps time resolution -Use the 16-channel PETIROC ASICs (available) : High bandwidth preamp (GBWP> 10 GHz), <3 mW/ch, dual time and charge measurement up to 2500 pe, jitter < 10 ps rms - Use a TDC with 25 ps time resolution (available) per ASIC (use the ∪ 16 available signal) - Design new PCB with pick-up strips - ASICs and the LB are on the same PCB (on the edge) the two strip’s ends are read out so one can have both hit position and time resolution OMEGA group

7. 24Ch 25ps TDC module Cyclone-II FPGA EP2C35F484C 6 100M Ethernet Readout with TCP/IP support Socket for TCXO (opt.) Differential input connectorTsinghua university

8. On-detector Strip Off-detector Strip  Strips are read out from both sides to get position and time measurement  The off-detector strips are on the edges (5-10 mm on each side?) and out of the detector  Strips are buried in an insulator layer. The PCB is to be inserted between two RPC.  ASICs and TDCs on one side. Limited zone is allowed.