Pixel Module Interfaces Mauro Citterio On behalf of INFN Milano

SVT System Integration SuperB SVT  similar to BaBar SVT + Layer 0 Layer 0 technology baseline for TDR  Hybrid pixels Still under study  maps for improved performances Each SVT layer is built of indepedent “modules” (52+8) One module is divided in two independent “half modules” Each half modules contains several “units”: Sensors Front-end chips Interfaces with power/signal input and data output link BUS and “smart HDI hybrid” Layer 0 is different form the other layers Layer 0

Layer 0 Bus Design Basic requirements: Prototype: SuperB specification Layer 0 BUS design derived by previous CERN experience with ALICE bus Aluminum-Kapton technology used SuperB specification High signal trace density  up to ~ 200 signal lines Data speed on each line  up to 160 MHz (parallel bus ~ 30 lines) Minimum thickness  maximum thickness ~ 220 mm Sensor/readout interconnection  by wire bonding Max current on a power plane  up to 5 Amp Carbon Fiber Support BUS Half Module: 6 MAPS Prototype: The tecnology data provided by CERN need to verified against the specs by means of a “simplified” BUS Various solutions on the same structure To compare simulation and actual BUS To test the technological limits

A “simplified bus” What is in the prototype (1.8 x 11.2 cm): Four layers  Stackup made of: Aluminum, polimide and glue 2 planes (each 50 mm thick), power and ground 2 signal layers Signal lines with and without corners on the same layer Signal lines on the two layers connected by means of minimum size vias Min Pads/Vias 150/50 mm Line widht: Min. ~ 75 mm, Max. 200 mm Lines with different overall lenghts, with and without bends Striplines and microstrips Differential lines

A “simplified bus” Microstrip Striplines Purple: top layer Orange: bottom layer Power/ground planes: not shown Diff. lines Dielectrics (polyimide + glue): 20 mm, 50 mm for 1st signal layer Impedance calculated to be 50 W in respect to first signal layer  FE driver to be designed accordingly lenght of top layer lines negligible  for impedance matching no “detailed” model for vias available  signal integrity affected ?

Impedance simulation (50 W) Data generated with CERN input The dielectric thickness adjusted to increase Z (~ 40 mm) Line widht at the “nominal” minimum (~75 mm) Line space could be reduced (~ 50 mm) but does not affect Z, it increases NEXT Not minimum thickness “Plane layers” minimum thickness is 50 mm  suggested by CERN to increase yield Because the Bus will operate at ~ 160-180 MHz  aluminum signal lines need to be plated by 2-3 mm of copper  overall thickness of lines estimated to be ~ 13 mm Total thickness of prototypes is 140 mm less than FINAL BUS which will have 2 more power planes

Updated estimate of final bus Not an “enclosed stackup”: Power plane must be on bottom Signal lines are assumed to be microstrips Better for speed, “high” impedance. Worse for far-end crosstalk and EMC If 200 signal lines needed  Three signal planes (two horizontal, one vertical) Using CERN "design rules" Digital ground Digital power supply Horizontal signal lines Vertical lines Analogue power Analogue ground 300 m for bonding on each bus side Glue 5µ Polyimide 15µ 399 µ Polyimide 40µ Aluminium 50µ Aluminium 13µ Aluminium 13µ

Impedance simulation at min. dielectric thickness Minimum dielectric thickness (15 mm) between signal layer and ground brings the impedance down to 30 W (w= 75 mm, w/h ~ 3.3, t << w) Z too low  will require a very high current FE output driver, unpractical

Signal Simulations with Hyperlinx To study the performance of the Bus, we have simulated the signal propagation using XILINX VIRTEX-5 driver and receiver: for which IBIS models are available because we plan to use these FPGAs in our test setup. In the figure an “ideal” scenario is shown: No bus Direct connection between driver and receiver Two overlapping signals are shown The signal has180 MHz frequency and 49 % duty cycle The shape is “extracted” by means of the IBIS models The driver sends out a 1.2 Volt signal

Signal Simulations: 50 Ohm BUS The bus is simulated by importing the stackup information An “end of line termination”, matching the impedance, is used The signal at the driver output is the “yellow” line The signal at the receiver input is the “blue” line The signal at the receiving end can still be read by the bus (logic level are matched) The simulation will be compared against real measurement as soon as we will have the “prototype bus”

Eye Diagram simulation: 50 Ohm BUS

Signal Simulations: 30 Ohm BUS The bus is simulated by importing the stackup information An “end of line termination”, matching the impedance, is used The signal at the driver output is the “yellow” line The signal at the receiver input is the “blue” line The signal at the receiving end can NOT be read by the bus it does not reach the High logical level The design of a minimum thickness is dropped, for the moment IMPEDANCE TOO LOW

NEXT simulation: 50 Ohm BUS Simulation consider “one” aggressor and one victim nearby. Signal on victim is approximately 30 mV at its peak Signal on victim is mostly due to the nearby aggressors NEXT ~ 3 % The simulation must be compared against real measurements on the prototype Bus

Ongoing Activity Layout of proto-BUS  completed Under review by the CERN design shop We hope to have the production to start soon The prototype will allow us to measure most of the “critical parameters” A measurement setup is under design, it will use adapter cards to connect Xilinx FPGAs to the BUS Production of the prototype is expected in 8-10 weeks The ball park figure is 6 KCHF 10 pieces is the minimum quantity for the run.

Still to be defined for a next version of the BUS Unspecified parameters For a realistic layout, PADs position on chip must be defined Evaluation of clock skew No “decoupling” on the BUS yet What is the tolerable Jitter Driver to be implemented in the IC must be able to load a 50 W bus ...... Power distribution: What is the tolerable drop on the power planes? Can we use a single power plane? by splitting it in two  substantial reduction in bus thichness (~ 70 mm)

Hybrid Design (optical solution) Hybrid Dimension (~ 13 mm x 70 mm x 15 mm)  for two optical links (total data rate ~ 10 Gbps) Some space need to connect hybrid and BUS ( < 1 cm2 ) Receiver, Glue Logic and memory under design  Xilinx Virtex family will still be used for prototyping (> 300 user defined I/O pins, RAM) First prototype of CMOS SRAM rad-tolerant memory received (~ 0.5 MB) and under test, result will reported soon ASICs for organizing/storing the data coming from the bus and to prepare the data for the serializer: design not started yet Serializer: plan to use IC called “LOC1” developed in SOS by SMU Dallas (2.5 Gbps) a LOC2 at 5 Gbps available by the end of 2009 Laser drivers: commercial (Texas and Micrel) devices and GBT-LD under investigation Duplex LC package for housing two VCSEL and fibers  SPACE is a concern To DAQ EDRO EPMC EPMC Optical Fiber 60/80 MHz

Hybrid Design (copper link) Elements on the hybrid: Share BUS data receiver, glue logic, memory and serializer of the “Optical link” solution Differs in term of output drivers we are acquiring evaluation boards for three different drivers from MICREL SY58600U (CML), SY58602U (400 mV LVPECL driver) operating up to 10.7 Gbps SY58601U (800 mV LVPECL driver) operating up to 5 Gbps typical copper link length ~ 3-5 m increasing the length means “high power”  not feasible Based on the results  2 or 4 copper lines solution on a maximum copper lenght Buffering Modulations Drivers Hp. All data out Cu bus < 20 Gbit/s Optical link 2.5 Gbit/s Edro like ROM Off detector low rad area Counting room On detector High rad area

Hybrid Design (mixed technology link !) Dictated by space constraints: Very likely not enough space for an optical link on the HDI near the detector The HDI will drive a short copper link Serializer must be capable of driving ~ 30 – 50 cm LOC does not incorporate such a driver The “transition card” will be active a “rad-tolerant” receiver must be found some work on going at CERN for IBL  to be investigated radiation level need to be understood  to investigate commercial solution, if any the combination <controls, laser driver, VCSELs, fiber optic packages> still the same volume on the transition card to be agreed upon Transition Card: Receiver +laser+VCSEL Optical link 2 x 5 Gbit/s Buffering Modulations Drivers Cu bus EDRO Near detector “medium” rad area Counting room On detector High rad area

Test set-up … under construction Data generated via FPGA Receiver + Glue Logic IC Design required if TDR approved Serializer Clock in Serializer Output Drivers Status: Fan out boards: under design FPGA boards: firmware in progress Hybrid: PCB design + evaluation boards Serializer: OK, LOC chips from Dallas + CERN Laser Driver: ordered (Micrel) VCSEL + package + fiber: ready to order  To be ready by the fall Copper cable: variable lenght Receiver and Laser Drivers VCSEL double LC package