1. A. Stabile – INFN Milano31 May 2010 XIII SuperB General Meeting - Isola d'Elba Bus, HDI and transition card for SuperB layer0 Alberto Stabile On behalf of INFN Milano and Università degli Studi di Milano

2. A. Stabile – INFN Milano31 May 2010 2/23 Main aim Transfer data from layer0 front-end electronics to DAQ to collect data and program FSSR2 (baseline) or MAPS (upgrade) to store data for 20 µs by means of buffers (hypothesis) to increase robustness using ECC codes and radiation hardening by design ASICs to transfer data at high frequencies (up to 5 Gbps!) to re-use similar approach for others layers (with less contraints)

3. A. Stabile – INFN Milano31 May 2010 3/23 Possible strategies (1/3) Usage of a passive HDI – Pros: few electronics devices inside radiation enviroment – Cons: high-densitity copper tail, drive capability and mechanical issues HDI size ≈ 1.0 TH x 14.8 W x 70 L mm Copper tail size ≈ 500 L mm → (≈ 100 lines) PIX/MAPS: Kapton/aluminum bus size ≈ 0.3 TH x 20 W x 45 L mm → ( ≈ 100 lines)

4. A. Stabile – INFN Milano31 May 2010 4/23 Possible strategies (2/3) Usage of a rad-hard IC containing up to six serializers (6:1) – Pros: cu-tail line reduction and possibility to re-use LOC serializer designed by SMU Dallas – Cons: frequency increase of data output lines (1.25 Ghz, 2 lines) HDI size ≈ 1.0 TH x 14.8 W x 70 L mm Copper tail size ≈ 500 L mm → (≈ 16 lines) – Hp: one diff. data out per FSSR2 PIX/MAPS: Kapton/aluminum bus size ≈ 0.3 TH x 20 W x 45 L mm → ( ≈ 100 lines)

5. A. Stabile – INFN Milano31 May 2010 5/23 Possible strategies (3/3) Usage a rad-hard IC containing data organizers, buffers, and serializers – Pros: copper lines and data rate reduction with HDI triggered by LV1 (optional) – Cons: radiation hardness HDI size ≈ 1.0 TH x 14.8 W x 70 L mm Copper tail size ≈ 500 L mm → (≈ 16 lines) PIX/MAPS: Kapton/aluminum bus size ≈ 0.3 TH x 20 W x 45 L mm → ( ≈ 100 lines)

6. A. Stabile – INFN Milano31 May 2010 6/23 MAPS vs FSSR2 FSSR2 has maximum 7 differential lines (not shared) and 7 differential lines (shared) – TOTAL = 98 interconnections on HDI New generation MAPS will have 16 single- ended lines for data (not shared) and ≈ 7 controls lines (shared) – TOTAL = 103 interconnections on the bus IT'S A MUST!! – Previous design had ≈ 200 lines Interconnection design comparison – Almost equal number of lines – Similar data output frequencies (140 MHz vs. 200 MHz) – BUT FSSR2 ON THE HDI AND NOT ON THE BUS! – Two different designs (not completely different → see next slides) – Differential approach could be pursued on MAPS (maximum frequency no more than 400 MHz – same number of lines)

7. A. Stabile – INFN Milano31 May 2010 7/23 On going activities We need to – Design the bus focus on PIX/MAPS upgrade 3 module design on going (see next slides) – Design HDI for baseline and upgrade Solution of choice should be third strategy (most challenging but comprehensive)

8. A. Stabile – INFN Milano31 May 2010 8/23 Bus for a 3-chip assembly (1/3) Layout of a BUS for up to 3 modules - using front-end IC “FE 32x128” (expected in the summer) - Bus widht: 8.7 mm - Signal trace layer widht: 75 µm - Bus length ~ 6.5 cm Issues accepted by CERN: - “Area opening” of 300x500  m possible on power planes to allow decoupling (cap mounting). The size of the openings is the “best results” on test structures - The stackup (layer and dielectric thickness) will be similar to the one used in the prototype bus. However multiple thin polyimide layers will be used to get “thick insulating” layers (to use same brand material everywhere)

9. A. Stabile – INFN Milano31 May 2010 9/23 Bus for a 3-chip assembly (2/3) Design guidelines – Each chip has its own signal data layer 3 chips → 3 layers Same impedance on each data layer (> 66 Ω) – Fourth signal layer shared by all chips Lower impedance ≈ 50 Ω – To decrease layout complexity and area, no vias have been used – 3 power planes + 3 ground planes 2 digital power/ground kept separated to avoid possible interferences – Data bus layout have been designed to reduce inter-bus capacitive values – Upgrade to 6 chips will scale accordingly Same number of layers

10. A. Stabile – INFN Milano31 May 2010 10/23 Bus for 3-chip assembly (3/3) Total thickness = 500 µm Single-ended lines The number of layers have to be reduced for a reasonable final design Design is going to be submitted to CERN for discussion No easy thickness improvement possible Clearly, this is a bus for study only

11. A. Stabile – INFN Milano31 May 2010 11/23 Bus cross section for final bus Digital ground Digital power supply Horizontal signal lines Analogue power Analogue ground Horizontal signal lines Glue 5µ Aluminium 50µ Aluminium 13µ Polyimide 40µ Polyimide 15µ 366 µ Reduction of lines in new PIX/MAPS IC submission It is necessary to have: – 2 layers for signals without vias – maximum 80 lines for each layer – 4 planes for power supplies

12. A. Stabile – INFN Milano31 May 2010 12/23 Third strategy: HDI Floorplan Better solution: third strategy is our baseline – Possibility to use LV1 to trigger data out of the SRAM buffer – Possibility to transfer all data to transition card – Deserializer needed only for FSSR2

13. A. Stabile – INFN Milano31 May 2010 13/23 Data Organizer Triggered solution – Use time stamp, and pixel position to generate SRAM buffer addresses – If LV1 trigger if affected by jitter, some problems could arise Solution: select 3 adjacent words Not triggered solution – Store all event inside a FIFO memory

14. A. Stabile – INFN Milano31 May 2010 14/23 Rad-hard buffer discussion Case study: FSSR2, easy to change for PIX/MAPS solution Latency = 5 µs Time to store data = 20 µs FSSR2 data output period ≈ 7.14 ns (140 MHz) Not triggered solution (FIFO approach): – Bit to store in 20 µs at 140 MHz ≈ 2800 bits – We have to store 180 words ≈ 2800/(24) Triggered solution (Indexed matrix approach): – To fetch the right addresses, we need a matrix architecture with 256 word-lines, 32 bit-lines and 16 different SRAM blocks – Time stamp = 100 ns – We store data for approximately 25.4 µs

15. A. Stabile – INFN Milano31 May 2010 15/23 SRAM triggered size 4 bits describing the row pixel number – 2 4 combinations → 16 SRAM blocks (16 data out) 8 bits describing the time stamp – 2 8 combinations → 256 word-lines (rows) 5 bits describing the column pixel number – 2 5 combinations → 32 bit-lines (columns) Single cell composed by 3 SRAM cells containing pulse height event data (option?)

16. A. Stabile – INFN Milano31 May 2010 16/23 Buffer floorplans

17. A. Stabile – INFN Milano31 May 2010 17/23 Buffer total characteristics Non triggered solution – Total buffer size (2.88 kbit * 6 FSSR2) = 17.28 kbit – Total ECC buffer size (3.84 kbit * 6 FSSR2) = 23.04 kbit Triggered solution – 384 kbit = 128*3 kbit (for 1 FSSR2) Very small memories Fast access time ≈ 10 ns (estimated on the size of SRAM blocks)

18. A. Stabile – INFN Milano31 May 2010 18/23 Radiation map

19. A. Stabile – INFN Milano31 May 2010 19/23 Radiation hardness techniques Radiation hardness by design can be achieved at different level of representation – Architecture level: Multiple bit upset → ECCs and block replication – Circuit level: Mitigation of Single Event Transient propagation – Layout level: Total Ionizing Dose → Edge-Less Transistors (ELTs) Latch-up → guard rings Upset → extra capacitors

20. A. Stabile – INFN Milano31 May 2010 20/23 Previous work: a rad-hard 512 kbit SRAM 64 kbit * 8 blocks 1.8 V CMOS technology Still fully functional up to 10 Mrad of dose Good level of radiation hardness with respect to upsets Latch-up immune Access time about 20 ns IC with new designs expected by end of June

21. A. Stabile – INFN Milano31 May 2010 21/23 Rad-hard serializer (5 GHz) LOCs1, at 5 Gbps 16:1 serializer designed in the SMU, Dallas, Texas → in Milano very soon, to be tested LOCs0 rad-hard up to 40 Mrad, at least Possibility to re-use this serializer for our purpose Need to investigate LOCs1 driver capability

22. A. Stabile – INFN Milano31 May 2010 22/23 Preliminary results: line driver for copper tail Set-up of a 16:1 serializer at 3 GHz using FPGA Xilinx Virtex 5 with RocketIO modules RocketIO has been used instead of SMU serializer Eye diagram BER probability density function

23. A. Stabile – INFN Milano31 May 2010 23/23 Conclusions BUS (only for MAPS) – 3 chip assembly submission to CERN by mid-July – Simulation of crosstalk and signal integrity have to be completed HDI – Third strategy is the most comprehensive solution – Deserializer, data organizer and SRAM buffer can be integrated in the same IC – Rad-hard design has recently started using 130 nm IBM CMOS technology Test of full chain are still going on – Very important is the test of SMU serializer!

24. A. Stabile – INFN Milano31 May 2010 24/23 Backup slides

25. A. Stabile – INFN Milano31 May 2010 Context

26. A. Stabile – INFN Milano31 May 2010 26/23 FSSR2 signals and power supplies Baseline with FSSR2... under discussion Data 2 differential input clocks (MasterA, MasterB) - shared 1 differential output clock from 1 to 6 differential and serial data outputs Program 1 shift-in (differential serial signal) - shared 1 shift-out (differential serial signal used to read parameter data) - shared 1 shift control to enable program mode - shared 1 differential BCO clock - shared 1 reset - shared Power supply 4 different power supplies (VDD, AVDD, GND, and AGND) - shared

27. A. Stabile – INFN Milano31 May 2010 27/23 Buffer access Triggered solution: We have to convert LV1 “information” in SRAM word-line addresses and read all cells corresponding to the LV1/word-line address Not triggered solution: Before to write new words. System have to read and transfer the old words

28. A. Stabile – INFN Milano31 May 2010 28/23 FIFO buffer size (not triggered) Possible FIFO buffer for each FSSR2 – 180 word-lines, 1 bit-lines, 24 data I/O blocks – 180 word-lines, 2 bit-lines, 12 data I/O blocks – 180 word-lines, 4 bit-lines, 6 data I/O blocks Possible FIFO ECC(32,24) buffer size – 180 word-lines, 1 bit-lines, 32 data I/O blocks – 180 word-lines, 2 bit-lines, 16 data I/O blocks (compatible with Jingbo serializer) – 180 word-lines, 4 bit-lines, 8 data I/O blocks

29. A. Stabile – INFN Milano31 May 2010 29/23 HDI deserializer HDI deserializer needed only for FSSR2 – Receive data from FSSR2 – Lock on the sync word – De-serialize words of 24 bit – Distinguish between sync word and event word Erase sync word Transmit event word toward the buffer

30. A. Stabile – INFN Milano31 May 2010 30/23 Preliminary results: line driver for copper tail Eye diagrams at 1.25 GHz using MICREL Sy5601 high-speed transceiver, receiver, and copper cables 50 cm M17/06 copper cable for high-frequency communications 130 cm low-cost copper cable

31. A. Stabile – INFN Milano31 May 2010 31/23 Jitter results Low-cost cable M17/06_R414 2 FPGA Frequency Period 1.25 GHz 800 ps 1.25 GHz 800 ps 3 GHz 333 ps PRBS127 Total Jitter254.75 ps28.95 ps101.68 ps Eye horizontal opening 545.25 ps771.05 ps231.65 ps Eye vertical opening 1.20 V1.21 V0. 668 V Eye amplitude LVPECL 1.26 V Differential 800 mV 1.27 V Differential 800 mV 0.796 V Differential 400 mV