1. SVT detector Electronics Status Overview: - SVT design status - F.E. chips - Electronic design - Hit rates and data volumes - Required ETD inputs Mauro Villa INFN & Università di Bologna 1

2. SVT Design Detectors: 5 Layers with Si Strips (z, phi, L1-L5); one high precision inner layer (L0) Open options for L0: striplets (45° strips), Hybrid pixels, MAPS Front-End Chips: 128 channels ASIC for strips, large (>10k) pixel area chip ROS: Layers are segmentend in phi (8-18) and z (2): 240 Read-Out Sections (ROS) 2

3. Strip/Striplet front-end chips  ASIC to be build based on previous experiences in several fields:  FSSR2 chip (analog part), SuperPix0, ApselXD (readout architecture)  CERN experience on specific blocks: Voltage regulators, serializers.  Develop fast (L0-L3) and slow (L4-5) channels (analog part tuning).  Triggered only chip with tunable time stamp characteristics.  Serialized output to reduce the I/O line count  Full VHDL simulation for TDR  prototype chips in 2012 & 2013;  production in 2014 POF: the first derandomizer is in FE chips 3

4. 4 DAQ reading chain for L0-L5 High rad area 15Mrad/year Off detector low rad area Optical Link 2.5 Gbit/s to ROM Counting room Std electronics FEB DAQ chain independent on the chosen FE options Optical 1 Gbit/s ~1-2 m LV1 HDI card design is ongoing Data Encoder IC.... Specs are under discussion Rad-hard serializer to be finalized  looking into a low power/low speed version Copper tail: lenght vs data transfer are under study FEB + ROM as before fibers Example of a read-out section Detector HDIs C Front-end chips Copper bus UPILEX+Cu (?) Transition card Serdes or FPGA 4

5. Detector – Connection HDI Low rate – 1 ouput line/FE chip High rate N lines/FEC Z φ Z Minimal number of elements on HDI (ideally only FE chips) 6 shared input lines: Reset, Clock, FastClock, Timestamp, Trigger, RegIn 1 shared output line: RegOut N lines x M chips in output (N:1-6, M: 4-10) 5

6. HDI and output bus Rad-hard characteristics dependent on chips –Requirement: > 5 Mrad/year Power dissipation: < 1 W/chip »(guess-estimate from previous experiences) High rate N lines/FEC φ Minimal number of elements on HDI (ideally only FE chips) 6 shared input lines: Reset, Clock, FastClock, Timestamp, Trigger, RegIn 1 shared output line: RegOut N lines x M chips in output (N:1-6, M: 4-10) Ground and powering on the bus Signal lines in standard LVDS (CMOS to/from LVDS required on HDI if not provided on FE) 6

7. Transition card Role of the Transition card: Provide an interface between FE and DAQ system Switch between copper and optical link data transmission Forward power to FE chips Off detector low rad area Serdes or FPGA Several open options: –Optical link Intrinsic dual link preferred: GBT (?), GOLx2 (?) Single link option possibile (data output link) together with a chip input data system (FCTS?) –Fast Des/Serdes SMU (Dallas), 5 Gbps, 500 mW (rad-hard) Other Des/Serdes ? FPGA (very interesting in principle, but not rad-hard [for the moment?]) 7

8. Low Speed / Low Power Serializer La Biodola 2011Mauro Citterio LOCs1 (mW)low power design CML Driver 9650% PLL17380% Others18730% The block schematic of the SMU LOC1 shows that the typical power of the chip (~ 500 mW at 5 Gbps) has a substantial contribution coming from the PLL circuit. A “Tunable” Serializer (data rate from 2.5 to 5 Gbps) can be obtained by changing the PLL. The goal is to reduce the power to ~ 250 mW at 2. 5 Gbps Simulation results indicate that (courtesy of SMU) : The final design/prototyping phase of this Low Speed /Low Power IC did not start, yet. SMU has received expression of interest by other experiment for such a development SMU is looking into opening a collaboration on such IC (technology is 0.25 um Silicon on Sapphire) 8

9. Data/Clock and Control Cables (1 of 2) La Biodola 2011Mauro Citterio 9 Kapton tail is probably not a solution for SuperB - data speed is much higher than before - differential/coaxial lines are not usually designed in flat circuits Some small and flexible cables have been selected and tests are on-going Some preliminary studies are ongoing (see M. Citterio talk in LONDON) - the reference lenght has been chosen ~ 1m (not to push on driving capability of devices) - the test has been performed using - Xilinx FPGA + Rocket IO as a reference - Xilinx FPGA + LOC1 serializer as a comparison 9

10. Data/Clock and Control Cables (2 of 2) La Biodola 2011Mauro Citterio 10 Signal: 30 AWG, Solid Copper Clad Aluminum Differential Impedance ~ 100 Ohms +/- 5% Capacitance: 16 pF / ft Propagation Delay: < 2 ns/ft The preliminary measurements show that LOC1 can drive such a cable without substantial degradation even without pre/post emphasis Eye diagram BER probability density function 10

11. SuperB-FEB Board schematics DAQ link 2.5 Gbit/s L1/Spare DAQ link 4x1 Gbit/s FE links Small FPGA Memory Large FPGA Gb ethernet VME FPGA Or uCPU VME! FCTS interface ECS interface FCTS, ECS protocols to be decided experiment-wide Large FPGA for data shipping and monitoring VME FPGA or uCPU might be included in the large FPGA. Request: 2 9U-VME crates Behind Rad-wall POF: the second Derandomizer is in FEB 11

12. Hit and Trigger generation and read out Bare Assumptions: –Readout clock: 60 MHz –Time stamp clock: 30 MHz –Trigger rate: 150 kHz –Fully triggered SVT –DAQ Acquisition window: 300 ns (L0-L3), 1 us (L4-L5) –Latency <10 us –Buffers in chip and in reading chain wide enough for eff>99.8% –Optical link 1 Gbit/s ; 2.5 Gbit/s to ROM –Background rates from latest BRUNO simulations with safety factors 5 12

13. SVT Background rates Background simulation:  Strip detail implemented in Bruno for a more accurate rate calculation Data volumes and bandwidths SVT data volumes and bandwidths are mostly independent on the details of the design, but are defined mainly by background, trigger rates and DAQ time windows. 13

14. SVT Data rates, links and boards LayerModulesHDI ReadOut Section (ROS) Grouped ROSFEBoard Plain rate Data to ROM/ FEBoard (Gbps) 081632 45.7 161224 24.3 261224 22.9 361224 21.7 41632643240.4 51836723640.4 Total/mean60120240172 181.9 Needs: 172 1-Gbps links, 18 Front-End Boards 2.5 Gbps links usable with load balancing connections (or data compression). Average event size: 24 kB. 14

15. 15 Conclusions SVT electronic has several open options at the moment - L0 type: striplet/hybrid pixels/MAPS - FE chips have to be designed (architectures ready, simulations ongoing) One fix: triggered only chips everywhere. Major unknowns: 1 Gbps optical link types (bidirectional? To be defined by ETD ) Serdes/FPGA(To be defined by ETD ) Front-end chip details (requirement document available) (several elements already designed) Additional active elements in the HDI (Rad-hardness tests to be made) Data chain is progressing by defining all the elements of the chain No showstopper seen in the “upper” part: FEB & ROMs. 15

16. Questionarie SuperB integration question naire Data: 5/11/2011 Sub detector name: SVT Author: Electronics: input from Villa Citterio Re Bettarini Number of electronic channel: 1) Internal chips: ≈2200 FE chip, 172x2 ser/des encoding, 172x2 optical link 2) 172 Transition boards at 1 m from SVT (just outside the detector?) 3) 18 FEB boards behind the radiation walls 4) Power supply boards outside (?) Power dissipated per channels: 1) 0.1 mW/chip, serdes and links to be decided 2) unknown 3) unknown 4) unknown Volume occupied by the electronics (drawings of electronic modules): 2) Design and exact place to be defined; 3) 2 9-U VME crates 6/12/2016 16

17. Questionarie Max tolerable distances between the detectors to the electronic modules: 1 meter between FE chips and Transition card 50 meters between Transition card and FEBs (in a VME crate) 10 meters between Power supply and Transition cards Access frequency on the external electronic per year: What are the needs? 2 times/year to measure I-V bypassing PS? ?? Frequency access on the detector per year: Only in case of accident 6/12/2016 17

18. Questionarie Cables: input from Citterio, Villa Number and size of power cable: input from babar are reasonable ? From inside to FEB and from FEB to PS Number and size of Read-out cables or fibers: Fibers: 172 bidirectional, 1 Gbps fibers, length 50 m (?) Fibers: 18 bidirectional, 2.5 Gbps fibers, length 3-5 m (?) Number and size of slow control cables: If bidirectional links, just clock distribution is needed. 172 special buses to go from transition card to FE chips. (1-2m with 1-2 cm width, <1mm thickness) Minimum bending radius. Shielding requirements (thermal and electrical) Citterio Information drawings on the cable distribution on the detector geometry: Can use babar schema as starting point 6/12/2016 18

19. Backups 19

20. Configuration and open options Striplets baseline option : –Better physics performance (lower material ~0.5% vs 1% hybrid pixel, MAPS or thin hybrid pixel in between but not yet mature!) Upgrade to pixel (Hybrid or CMOS MAPS), more robust against background, foreseen for a second generation of Layer0 Layer 0 40 cm 30 cm 20 cm Layer0 Layer Radius 0 ~1.5 cm 1 3.3 cm 2 4.0 cm 3 5.9 cm 4 9.1 to 12.7 cm 511.4 to 14.6 cm Layer Radius 0 ~1.5 cm 1 3.3 cm 2 4.0 cm 3 5.9 cm 4 9.1 to 12.7 cm 511.4 to 14.6 cm Triggered FE chips Layer 1-5 Strip detectors (up to 37 cm long) Triggered FE chip in the design phase 20

21. SVT- Electronic status Striplets baseline option : –Better physics performance  Readout chip in the planning phase –Upgrade to pixel, more robust against background, foreseen for a second generation of Layer0  Readout chip designed Layer 0 Triggered FE chips Layer 1-5 Strip detectors  Readout chip in the planning phase Triggered FE chips FE Ctrl logic Buf #k... Buf #1 ADC Or ToT BUF #1 readout/slow control strip #127 strip #0 FE Ctrl logic Buf #k... Buf #1 ADC Or ToT Sparsifier ~hit_rate * trig_latency Triggered hits only Strip RO chip DAQ Chain main activities RadHard SerDes needed 21

22. Pixel front-end chips (L0) Full design of a 256x192 pixel matrix (50 um pixel width) running at 70 MHz; Timestamping at 100 ns; output clock at 200 MHz Data push or data pull selectable working mode 1 2 X4 22

23. Efficiency for triggered version In triggered mode, hits stay on matrix till readout (trg on TS) or clear -> increase of occupancy and dead area -> inefficiencies Reduction of bandwidth: from 2.6 Gbps to 40 Mbps (using standard test values: 100 MHz/cmq rate, 150 kHz trig rate, 0.3 us DAQ window) 50 MHz clock 2.5 MHz trigger rate (demanding!) Eff(6 μs) = 98.16% 23

24. Apr. 2011Mauro Citterio 24 1-st prototypes results Pixel Bus Prototype measurements:  Thermal test on the BUS did not show problems up to 85-90 Centigrade  A typical impedance of ~ 60 Ohm confirmed  Crosstalk higher than simulated ~ 5 %  Measurements performed on various samples with same results  frequency response:  signal transferrred with no “digital errors” up to 200 MHz, on individual lines (pattern ex. 0000100)  if a random digital pattern is sent through 8 adjacent lines, than max frequency decreases at ~ 160 MHz (line lenght ~ 10 cm) Bus for pixel chips M. Citterio Aliminum on kapton 165 um 24

25. Bus for pixel chip - II Pixel Bus second generation:  Layout details agreed  Production: it could have started week 7  Production conclusion estimate  8-10 week later  Cern suggestions: Review the signal layers: concern about 15 um Al layer and 75 um lines prefer a BUS with decreased thickness Adoption of Cu (3 um thick, 50 um wide) Two IC signals will share the same plane Simulation performed -on a 1101 pattern (three aggressors and one victim, the “0” line) -The results refer to the longest stripline. Goal was to keep the crosstalk signal below +/- 200 mV The maximum frequency is ~ 130 MHz There is no optimal termination at the receiving end. Driver and receiver are implemented using the IBIS models provided by Xilinx BUS bandwidth is decreased by ~ 15 % It is the worst case ? M. Citterio 25

26. FE Ctrl logic Buf #k... Buf #1 ADC Or ToT BUF #1 readout/slow control strip #127 strip #0 FE Ctrl logic Buf #k... Buf #1 ADC Or ToT Sparsifier Readout chip for strips ~hit_rate * trig_latency First buffering per strip then transfer triggered time stamps Triggered hits only Re-use of digital readout logic developed for pixels 26

27. Analog part: ENC, shaping time and efficiency estimates LayerC D [pF]t p [ns]ENC from R S [e rms] ENC [e rms] Channel width [  m] Hit rate/strip [kHz] Efficienc y 1/(1+N) 011.225220680145020600.890 126.7 5065011903010 268 0.969 10046093037700.940 231.250830140033001790.979 345.85014802130412052.50.994 452.610003408201137021.90.950 567.5100050010101350018.70.957 RC 2 CR shaping, I D =500  A (current in the PA input device), L=200 nm, N-channel input device, analog dead time=2.4 t p V. Re27SuperB Workshop, Frascati, April 4, 2011 27

28. First guess on number of buffers required for L0 striplets/L1 strip Assume L0 @ 225 MHz/cm2, L1@5 MHz/cm2 –L0 = 2 MHz/strip, L1=270 KHz/strip F. Morsani 28

29. 29 DAQ reading chain for L0-L5 High rad area 10Mrad/year Off detector low rad area ROM Optical Link 2.5 Gbit/s Counting room Std electronics FEB HDI +Transition card+FEB+ROM DAQ chain independent on the chosen FE options Optical 1 Gbit/s ~50 cm LV1 HDI and transition card to be designed. Which SerDes? 29

30. Optical link mezzanine card for EDRO Developed as a part of ATLAS/FTK project 4 optical links at 1 Gbit/s; FPGA Xilinx, 40/100 MHz clk (programmable) PCB realized; now mounting components on first prototype Usable as link test mezzanine in SuperB (from autumn) 30