1. Update on SVT electronics
G. Rizzo - INFN and University, Pisa
M.Citterio-INFN Milano
on behalf of the SVT Group
ETD Parallel Session
SuperB Workshop - SLAC 2009
Oct 6-9, 2009
G. Rizzo
SVT - ETD Session - SLAC Oct

2. SVT - ETD Session - SLAC Oct. 8 2009
SVT System
SuperB SVT  similar to BaBar SVT + Layer 0
Layer 0 technology (baseline for TDR)  Hybrid pixels (50x50 mm2 pitch)
Still under evaluation for layer 0: MAPS and Pixel V_I for improved performances
Layer 1- Layer 5  double sided silicon detectors 300 um thick
Each SVT layer is built of indepedent “modules” (52+8)
One module is divided in two independent “half modules”
Each half modules contains several “components”:
Sensors
Front-end chips
Interfaces with power/signal inputs and data output link
Layer 0: BUS and “HDI hybrid”
Other layers: hybrid/readout ICs
Module support/cooling
Layer 0
G. Rizzo
SVT - ETD Session - SLAC Oct

3. SVT baseline configuration (1)
Layer Radius cm cm cm cm
to 12.7 cm
to 14.6 cm
Layer 0: Hybrid Pixels
Radius: ~ 1.5 cm
Module length: ~ 10 cm
Pixel Pitch: 50x50 mm2
Hit Rate: MHz/chip (safety factor=5)
Module Rates: MHz
Link Bandwidth: 20 Gbps Full Rate (FE data push)
3 Gbps Triggered Rate
Power consumption: ~ 2 W/cm2 in the active area
~ 50 (mW/Gbps)/cm2 in HDI
Total material budget: ~ 1% X0
Si sensor + FE chips % X0
Al Bus + SMD comp % X0
Support & cooling ~ 0.3 % X0
Carbon Fiber Support
BUS
Half Module: 6 FE chips
HDI: ~ 13 x 70 mm2
Power/Signal
Data
G. Rizzo
SVT - ETD Session - SLAC Oct

4. SVT baseline configuration (2)
Layer Radius cm cm cm cm
to 12.7 cm
to 14.6 cm
External Layers: Double sided silicon detectors 300 um thick
Radius: BaBar radii for the 5 layers
Module length: similar to BaBar radii for the 5 layers
Structure: L1-L2-L3 barrel shape
L4-L5 arch shape
Extend coverage down to 300 mrad FW and BW
In BaBar it was 300 mrad FW and 520 mrad BW
Link Bandwidth: < 1 Gbps Full Rate (FE data push)
< 100 Mbps Triggered Rate
Power consumption: ~ 1 W/cm2 in HDI
Work ongoing using IC (FSSR2) that will require some modifications for SuperB
HDI design partly “inherited” by the layer 0 HDI design
Need to check those numbers for L1-L2 with the new back. evaluation
HDI
Si Wafers
Data
Power/Signal
Front-end chips
G. Rizzo
SVT - ETD Session - SLAC Oct

5. SVT - ETD Session - SLAC Oct. 8 2009
Main SVT challenge: Layer 0 thin/fast/rad tolerant
Background rates  FE chips, data bus and data transmission
Update on the various items in the next slides
Layer1-5 are less demanding:
solution adopted for Layer0 (in the link between the HDI and DAQ) can be inherited
FE candidate chips FSSR2 data driven
L1-L5 data could be used in LV1 trigger…
G. Rizzo
SVT - ETD Session - SLAC Oct

6. Layer0 pixel Front-End chip
Develop front-end chip for high resistivity pixels with
50x50 um2 pitch & fast enough readout to cope with background.
Use data push readout architecture developed for MAPS chip, now optimized with target rate 100 MHz/cm2 on full chip size (~1.3 cm2)
Space time coordinates with time granularity us (BCO clock)
Prototype chip (32x128 pixels) submitted as we speak: ST 130 nm process
Lab test in 2010  Testbeam (FE chip+sensor bump bonded) Sept
VHDL FE chip simulation:
Readout Efficiency > 60 MHz RDclock
Need ~ 160 MHz clock on the parallel output bus
FE chip Layout (32x128) – preliminary
G. Rizzo
SVT - ETD Session - SLAC Oct

7. SVT - ETD Session - SLAC Oct. 8 2009
50 mm
Cell Layout
S/N ~ 100 for 200 um thick sensor
G. Rizzo
SVT - ETD Session - SLAC Oct

8. SVT - ETD Session - SLAC Oct. 8 2009
FE Chip architecture
Each readout sweeps a portion of the matrix with 60 MHz clock.
Data from the final barrel are sent to a common bus with a faster clock ~ 160 MHz
G. Rizzo
SVT - ETD Session - SLAC Oct

9. Layer 0 Bus Design Basic requirements:
Layer 0 BUS design derived by previous CERN experience with ALICE bus
Aluminum-Kapton technology used
SuperB specification are challenging
High signal trace density  up to ~ 200 signal lines
Data speed on each line  up to 160 MHz (parallel bus ~ 30 lines)
Minimum thickness  goal for thickness < 300 mm
Sensor/readout interconnection  by wire bonding
Max current on a power plane  up to 5 Amp
only 10 MHz on ALICE Bus
Using CERN "design rules"
Impedence 50 W
300 m for bonding on each bus side
Digital ground
Digital power supply
Horizontal signal lines
Vertical lines
Analogue power
Analogue ground
Glue 5µ
Polyimide
15µ
290 µ
Polyimide
40µ
Aluminium 25µ
Aluminium 10µ
Aluminium 10µ
G. Rizzo
SVT - ETD Session - SLAC Oct

10. Status of the “simplified bus”
The delivery of the prototype (1.8 x 11.2 cm) was delayed (!)
 now expected by Oct. 23, 2009
CERN Technology Stackup made of: Aluminum, polimide and glue
Various lines on the same structure to compare simulation and actual BUS
To test the technological limits in term of frequency (signal up to 160 MHz, 32bit BUS)
Four layers bus 2 planes (each 25 mm thick)  power and ground + 2 signal layers
Min Pads/Vias 150/50 mm
Line widht: Min. ~ 75 mm, Max. 200 mm
Waiting for real measurements on the Al bus…signal Integrity Simulations (with Hyperlinx) shows encouraging results:
The signal (160 MHz) at the receiving end can still be read (logic level are matched) even in the worst case scenario (no termination)
G. Rizzo
SVT - ETD Session - SLAC Oct

11. Signal Integrity Simulations with Hyperlinx
To study the performance of the Bus, we have simulated the signal propagation using XILINX VIRTEX-5 driver and receiver:
for which IBIS models are available
a driver/receiver similar to the one expected in the front-end electronics is used (LVCMOS12_S_8)
these block will be used in our test setup.
In the figure an “ideal” scenario is shown:
- Termination at the receiving end, based on the bus impedance
The signal has160 MHz frequency and 49 % duty cycle
The shape is “extracted” by means of the IBIS models
The driver sends out a 1.2 Volt signal at 8 mA
G. Rizzo
SVT - ETD Session - SLAC Oct

12. Signal Simulations: no termination
The bus is simulated by importing the stackup information:
-overall line + receiver are equivalent to a Cload ~ 12 pF
(Tr ~ 2 nsec)
No end of line termination used
The signal at the driver output is the “yellow” line
The signal at the receiver input is the “blue” line
The signal at the receiving end can still be read (logic level are matched), however the signal has very large distortion
G. Rizzo
SVT - ETD Session - SLAC Oct

13. Signal Simulations: series termination
In case that a line termination at the receiving end is not feasible, then the signal integrity can be recovered by adding a serie resistance at the receiving or driving (better result BUT difficult to implement) end of the bus.
G. Rizzo
SVT - ETD Session - SLAC Oct

14. Receiver +laser+VCSEL
HDI Design Progress
Mixed technology - Cu+optical link solution seems more affordable:
storing data on the HDI (serializer: LOC chip is a possible choice)
Short (30-50 cm) Copper link between HDI  transition card
optical link in medium rad. tolerant area: transition card  DAQ
On detector
High rad area
Near detector
“soft” rad area
Counting
room
EDRO
Optical link
2 x 5 Gbit/s
Cu bus
Glue Logic
L1 time Buffer
Serializer (5 Gbit/s)
Transition Card:
Receiver +laser+VCSEL
The “transition card” (size ????, rad levels???) must be active
a “rad-tolerant” receiver not identified
IBL at CERN  receiver IC is going to be designed
A survey of commercial solution should be undertaken
Laser drivers: commercial (TX L2701and Micrel SY88992L) devices and GBT-LD need to be investigated, Duplex LC package for housing two VCSEL and fibers
G. Rizzo
SVT - ETD Session - SLAC Oct

15. SVT - ETD Session - SLAC Oct. 8 2009
Serializer
Even if an FPGA Control board based on Xilinx Virtex will be used for prototyping we have intiatiated a test campaign on “special components”
In particular we have started testing a Rad-hard serializer
“LOC1” developed in SOS by SMU Dallas (2.5 Gbps)
The IC is not really “user-friendly”  is an IC “in progress”
Electrical specification
Input power supply: 2.5V (Analog/Digital), 3.3V VCSEL
Power consumption ~200mW  high !!
Input data signals LVCMOS 2.5V
Reference clock 62.5MHz  optimized for LHC
20bit 8B/10B encoded input data
Some problems encountered (and confirmed by the designers)
The differential signal amplitude is about 240mV, measured by a differential probe. This is much lower than the 400 mV design spec.
The rise and fall times show a data pattern dependence. They are measured to be around 150ps. This is boarder line for 2.5 Gbps signal.
The reasons for the above problems are not completely known.
The device can be used for testing but we really need the LOC2
chip (expected by November 2009) with all problem solved, hopefully
Eye diagram of the Input 27-1 Pseudo random data.
UI = 400ps, for 2.5 Gbps.
G. Rizzo
SVT - ETD Session - SLAC Oct

16. SVT - ETD Session - SLAC Oct. 8 2009
link
Other commercial interesting solutions:
Aeluros, Inc.: “standard 0.13 μm CMOS”
esilicon: “, 10.5 Gbps Serdes in 90 nm and 65 nm CMOS, TSMC”
Prism Circuits, Inc.
Fujitsu 65 nm HP process
Multi-rate 3.125Gb/s to Gb/s
Low jitter LC-PLL supports up to 8TX unidirectional lanes
1.25W per Gb/s (this is too good, need to check).
Other component to be studied:
Laser drivers: commercial (TX L2701and Micrel SY88992L) devices and GBT-LD  not yet started
Duplex LC package for housing two VCSEL and fibers  seems OK, follows CERN development
G. Rizzo
SVT - ETD Session - SLAC Oct

17. Test set-up … still under construction
Data generated via FPGA
Receiver + Glue Logic emulated via a custom made controller board
designed in collaboration with Sanitas EG
 should be completed by end of the year
Clock in
Serializer
Serializer
Other parts:
LINK: small progress on LOC
Serializers: commercial components not yet received. Expected by end of October
Laser Driver: we are still deciding what to evaluate
PCB design: frozen until we can complete the test of other serializers
 goal: have a minimal system operating by end of the year
Output Drivers
Copper cable: variable lenght
Receiver and Laser Drivers
VCSEL double LC package
G. Rizzo
SVT - ETD Session - SLAC Oct

18. SVT - ETD Session - SLAC Oct. 8 2009
Summary
Front-end prototype chip for hybrid pixel “in production” . Test in 2010.
Prototype Al bus: should be available soon
We are ready to start testing the electrical characteristics of the bus
Mixed link solution: some tests on LOC serializer, more devices need to be tested
Link Test setup in progress
FPGA part is progressing well even if with some delays
Other parts: moves slowly, awaiting some crucial part to take decisions on PCB design
G. Rizzo
SVT - ETD Session - SLAC Oct

19. SVT - ETD Session - SLAC Oct. 8 2009
backup
G. Rizzo
SVT - ETD Session - SLAC Oct

20. Bus Impedance simulated to 50 W
Data generated with CERN input
The dielectric thickness adjusted to increase Z
(~ 40 mm)
Line widht at the “nominal” minimum (~75 mm)
Line space will probably be reduced to ~ 50 mm
 it will not affect Z
 it will increases NEXT (~ 4.5 %)
Not minimum thickness
“Plane layers” thickness has been reduced from 50 mm to 25 mm
Aluminum signal lines has been also reduced from 13 mm to 10 mm
Total thickness of prototypes is expected to be ~ 160 mm
G. Rizzo
SVT - ETD Session - SLAC Oct

21. SVT - ETD Session - SLAC Oct. 8 2009
EDRO Readout board
Front End Card used in Slim5 beam test (SVT par. II):
Main concept: flexibility at all levels
Mezzanines to decouple input/processing/output
Large FPGA
Several triggering schema
Slink
To DAQ
SuperB:
60 Mhz bus clocks
20 Gbit input rate
2.5 Gbit output rate
New board version
under design
Performances:
40 Mhz bus clocks
8 Gbit input rate
1 Gbit output rate
2.5 ME/s
40 kHz DAQ
Data from
FE chips
4 Gbit/s
EPMC
Stratix
EPMC
TTCRQ
Not too far from SuperB needs
G. Rizzo
SVT - ETD Session - SLAC Oct