1. Mauro Citterio, Fabrizio Sabatini
Peripheral Electronics
Mauro Citterio, Fabrizio Sabatini
INFN Milano
2 June 2012
Mauro Citterio - SVT Parallel - Elba Meeting

2. DAQ reading chain for L0-L5
Optical 1 Gbit/s
Front-end chips
Optical Link
2.5 Gbit/s to ROM
UPILEX+Cu (?)
FEB C
Copper bus
Serdes
or FPGA
ROM
Detector
fibers
HDIs
< 1 m
LV1
Transition card
High rad area 15Mrad/year
Off detector
low rad area
~ 5Krad/year
Counting room
Std electronics
Area of interest  fanout (layer0)
 Copper bus brief update
 Transition card  work is focused on thermal
analysis of the boards (Simone Coelli presentation) 2

3. Mauro Citterio - SVT Parallel - Elba Meeting
Fanout (layer 0)
To be addressed in the design:
Fit existing CAD model
max width 29 mm
Provide a “general” layout outline
Bonding always toward detector side
Detector
General Layout Outline
Requirements:
“Cut-out” profiles for bonding on detector long sides (both sides)
Vertical position of “opening” determined by detector size
Only one Opening needed
Cut-out/Openings dimensions set by technology (baseline is CERN)
2 June 2012
Mauro Citterio - SVT Parallel - Elba Meeting

4. Mauro Citterio - SVT Parallel - Elba Meeting
Fanout (layer 0)
Min. pitch calculation for various condition
w/wo constraints on trace/IC channel matching
Avoid multiple and/or excessive narrow pitches
Min. pitch safe for Copper, maybe doable for Aluminum
R and C estimated only on a realistic layout
13.1
29.0
COPPER or ALUMINUM Fanout Design Details
Maximum Lateral Dimension (mm) 29
Cut out (mm) 1
Later dimension above Cut-out (mm)
13.1
Constraints on having 128 adjacent traces on each IC
Layers
L1 (bottom Layer)
L2 (top Layer)
128 ch on L1 (over sensor)
128 ch on L2 (over sensor)
Overall Widht (mm)
29.00
Distance of last trace to border (2 sides) (mm)
0.60
0.3
Clearance around Cut-out (common to both Layers) (mm)
0.90
0.6
Clearance around Cut-out (additional for L2) (mm)
Cut-out
1.00
Total "available" widht/layer (mm)
26.50
25.90
12.20
11.60
Single Layer Solution
Dual Layer Solution
Pitch calculation with constraints applied
L1 + L2 (over sensor)
L2 (over sensor)
Remaining widht
Overall Available widht (mm)
52.40
23.80
11.6
28.60
Number of traces
768
256
128
512.00
HV + GND traces 2
Pitch (mm)
0.0340
0.0680
0.0920
0.0906
0.0559
Best choice
2 June 2012
Mauro Citterio - SVT Parallel - Elba Meeting

5. Mauro Citterio - SVT Parallel - Elba Meeting
Fanout (layer 0)
Absolute reference point (0,0) in scaling detector size and layout
Detector structure obtained from existing GDS files
Detector-pads pitch properly scaled
More strip than IC channels ….. Just a few !
2 June 2012
Mauro Citterio - SVT Parallel - Elba Meeting

6. Mauro Citterio - SVT Parallel - Elba Meeting
Some detectors PADs in the corner not necessarily connected (very short strips, No. of IC channels exceeded
Absolute reference point (0,0) in scaling detector size
Some detectors PADs in this corner not connected, too
2 June 2012
Mauro Citterio - SVT Parallel - Elba Meeting

7. Mauro Citterio - SVT Parallel - Elba Meeting
Fanout (layer 0)
A layout has been completed based on those requirements
Two layers with the “general” layout outline previously described
Trace pitch is 68 um, “soft corners” used
The traces are staggered plane to plane
Detector
Inner Layer
Outer Layer
Some details:
Each layer carries 768 traces (384 routed to the “left”, 384 routed to the “right”
Each layer on the “right side” of fanout has 170 traces over the opening and 214 traces below it
the 128 channel multiplicity is broken, one IC reads two block of NOT contiguous strips
Detector Bias provided on the fanout side without the opening
Gerber Files uploaded in the agenda page for evaluation
2 June 2012
Mauro Citterio - SVT Parallel - Elba Meeting

8. Mauro Citterio - SVT Parallel - Elba Meeting
Opening details
Detector
Some details:
170 traces are bonded on each layer through the opening ~ 1mm wide
Staggering of traces between planes is partially lost due to bend and different pitch between detector and fanout
Moreover bonding near detector corner is critical, only few traces
Almost 450 um have been considered for opening clearance
2 June 2012
Mauro Citterio - SVT Parallel - Elba Meeting

9. Mauro Citterio - SVT Parallel - Elba Meeting
Inner Layer structure
Inner Layer
Some details:
Each trace, at the termination, has been bended to face 45 degree detector pad
Grid and bending angles should not be a problem in manufacturing
Pad on each trace has a length of ~ 200 um
For multiple bonding, if necessary
Finishing of pads depends from conductor used for bus. Use of gold should be limited
The layout is being checked for “inconsistencies” or errors. Not showstopper observed up to now.
2 June 2012
Mauro Citterio - SVT Parallel - Elba Meeting

10. Bias Distribution (inner layer)
Outer Layer
Detector
Bias well separated from other traces >150 um.
Additional checks required, near the detector (where the bonding will be?) and on the HDI (what is the exact position of ICs?)
Note: IC dimensions should be ~ 6 x 4 mm.
IC bonded to fanout on the longest side (6 mm)
2 June 2012
Mauro Citterio - SVT Parallel - Elba Meeting

11. Mauro Citterio - SVT Parallel - Elba Meeting
Fanout in HDI area
Detector
Some details:
The proposed layout does not take real advantage of the bended extension of the HDI in front of the ICs.
To gain space for the Fanout traces, it could be better to move back some more the ICs on the ceramics.
The HDI drawings are only a model to be reviewed.
5-6 mm of overlap between HDI and fanout has been taken as a reference.
Exact pitch adjustment/compensation in front of the ICs difficult due to “not standard” angle of ICs in respect of detector
2 June 2012
Mauro Citterio - SVT Parallel - Elba Meeting

12. Mauro Citterio - SVT Parallel - Elba Meeting
Choice of materials
From Nicola Neri presentation ………
2 June 2012
Mauro Citterio - SVT Parallel - Elba Meeting

13. Copper Output Bus Update
Proposal: a 3 layer Copper/Kapton tape to carry all LVDS lines from and to the front-end ICs.
Aspect ratio: ~ 10 mm x mm
At the connector the tape is ~ 17 mm wide.
Update: Separate LV and HV cables !!!!
More LVDS data lines
Connector not really rated for the current needed by our frontend ICs (overheating)
Serializer on the HDI still a possibility, however the baseline is shifting more and more towards multiple LVDS lines (~ 180 MHz) up to lines
 More info in Mauro Villa presentation
Output connector has 0,4 mm pitch.
Goal is to use 70 contacts connector.
It could be increased to 80 contacts.
It will carry all LVDS lines
2 June 2012
Mauro Citterio - SVT Parallel - Elba Meeting

14. Mauro Citterio - SVT Parallel - Elba Meeting
Width of Copper bus is determined by geometrical reasons:
Dimension of Transition Card
Routing of Bus (an example is shown on bottom)
2 June 2012
Mauro Citterio - SVT Parallel - Elba Meeting

15. To be reviewed: no more power
Copper Bus Structure
Stack-up Design Rules:
LVDS Lines: Strip lines
LVDS Lines: 4 mils
LVDS Space: 4 mils
LVDS Copper Thickness ~ 20 um (~½ ounce)
Dielectric Thickness: ~ 100 mils
Zdiff ~ 100 Ohm
To be optimized
Kapton Thickness: 2 mils (?)
Via Diameter: mils
Via Clearance: 6 mils
Power/Gnd Planes:
Widht ~ 4.7 mm (almost double for GND !!)
Thickness > 50 um (or 2 ounces)
Current capability ~ Amps
Voltage drop (both ways) ~ 250 mV
GND
LVDS
Power
GND
LVDS
Power
To be reviewed: no more power
2 June 2012
Mauro Citterio - SVT Parallel - Elba Meeting

16. Mauro Citterio - SVT Parallel - Elba Meeting
Summary
Activities in Milan were mostly focused on the fanout design (layer 0):
A layout has been completed
The gerber files are available
We hope that people can review the layout and provide us with a feedback
The goal is to finalize the layout and produce few prototypes in Copper (a well established technology)
In parallel we will try to pursue a reduction in X0 by
Using Aluminum instead of Copper (same layout)
Push thickness of Copper and Kapton to the limits
The Copper Output Bus need to be modified
It will contain only LVDS lines
The goal is to optimize performance with a large number of LVDS lines
In parallel we will try to identify a possible power/HV connector to be mounted on the HDI and transition card together with the Panasonics one.
2 June 2012
Mauro Citterio - SVT Parallel - Elba Meeting

17. Mauro Citterio - SVT Parallel - Elba Meeting
2 June 2012
Mauro Citterio - SVT Parallel - Elba Meeting

18. Mauro Citterio - SVT Parallel - Elba Meeting
Fanout (layer 0)
Absolute reference point (0,0) in scaling detector size
Design on Copper/Kapton 2 layer fanout
Fanout min. pitch necessary is ~ 56 um  Decided to use 50 um
Bonding always toward detector side
Constrains applied: traces match IC channel sequence
Fanout resistance estimate is still approximate ~ 0.85 ohm/cm (assuming Aluminum resistivity ~ 33 ohm x m x 10-9). Capacitance not yet estimated.
Narrow pitch needed over a length of ~ 50 mm
Cern suggestions:
Minimize the area where the pitch is 71 um
Perform a test on one layer to verify reliability/consistency of pitch
Concern about bending such a fine lines (perform resistance test before and after bending) on first sample
Spread lines before reaching bonding
Overall fanout width 33 mm  It should fit in the existing CAD model of detector
2 June 2012
Mauro Citterio - SVT Parallel - Elba Meeting