1. SVT detector electronics
Mauro Villa
INFN & Università di Bologna
Overview:
- SuperB SVT
- Front End chips
- Layer 0 peculiarities
- SVT channels and rates
- Data transmission
- SVT in trigger and DAQ schemas

2. SuperB SVT
40 cm
30 cm
20 cm
Layer0
Layer Radius cm cm cm cm
to 12.7 cm
to 14.6 cm
Baseline: use an SVT similar to the BaBar one adding a Layer 0
Layer 0 options: striplets or thin pixels (40x40 um^2).
Each layer has several modules, mechanically independent units (52+8)
Each module has 2 half-modules, electrically independent units:
Sensor, front-end chips, HDI with power/signal input and data output link
Pixel half-module
Strip(lets) half-module
Data
Pixel sensor +
front-end chips
HDI
Power/Signal
HDI
Si Wafers
Data
Power/Signal
Front-end chips
Paris, 16/02/09
M. Villa

3. Data driven vs triggered FE chips
Data Driven chips
FSSR2: only minor modifications needed for SuperB
MAPS: no storage of data in local high radiation environment
Could allow to use SVT data for LV1 trigger
Need very fast link to send all data from HDI to DAQ (layer 0 critical! See next tables)
Triggered chips
Sending off chip only data from LV1 evt reduces by ~ 1/10 the load to the data transmission
Need to investigate if there is a good match for striplets!
MAPS readout: data out of high rad desiderable. Data stored outside vertex region in custom high rad memory chips.
Pixel sensor +
front-end chips
Off Detector
HDI
Power/Signal
DAQ
Data
HDI
Power/Signal
Very Fast link
DAQ
On Detector
Paris, 16/02/09
M. Villa
link
Data

4. Layer0 peculiarities
Rad hard environment
Large machine background ( 15 mm from beam line)
Fundamental the first point of a track for vertexing
Option under study: strip or pixel sensors (40 um pitch)
Apsel6D – or similar
320x216 pixels a 40 um pitch.
Active Area = 110 mm2
Completely data driven architecture
Space time coordinates
Time granularity us
(1.0 us is the goal)
External Time stamp clock.
Hit rate expected: 110 Mhit/s/chip
(with a safety factor>5).
Paris, 16/02/09
M. Villa

5. SuperB Layer 0 Module Plan: 2009-2010 Production of a test module
6 Chips: 1.1 cm^2 Signal lines: 180 in 1 cm width
Hit Rate: 110 MHz/chip (safety>5)
Module Rates: 660 MHz
Bandwidth: 20 Gbit/s (design parameters)
Thin aluminium bus for power and signals
Main technological challenge:
Line spacing (<100 um)
Frequency (> 100 MHz)
Plan:
Production of a test module
With 2-3 APSEL5D chips Electric and beam tests
Paris, 16/02/09
M. Villa

6. SuperB SVT in numbers 6 layers: Layer0 + 5 layers like BaBar SVT
Modules
HDI
ReadOut
Section (ROS)
chips/ROS
chips
channels
0- Striplets 8 16 32 6
192
2.46E+04
0- Pixels
12.59E+06 1 12 24 7
168
2.15E+04 2 3 10
240
3.07E+04 4 64 5
288
3.69E+04 18 36 72
324
4.15E+04
total 60
120
1316
12.97E+06
Track layer0: 5.3 GHz (safety factor 5 included)
fully dominated by machine bkgd
Paris, 16/02/09
M. Villa

7. Load to the data transmission
Requirements on link speed reduced by 1/10 Assuming 1 us window and 100 KHz LV1 rate
Simulated Background rate x20
(cluster multiplicity and safety factor)
Layer
flux
(Hz/cm2)
1 us
occupancy
HDI Link speed
Read all data
Data driven
( bit/s/ROS)
Read only LV1 evt
(bit/s/ROS)
hit/evt
bit/evt
(with 25 bit word)
0- Striplets
1.00E+08
9.00E-01
1.73E+10
1.73E+09
2.21E+04
5.53E+05
0- MAPS
2.50E-03
1.64E+10
1.64E+09
2.10E+04
5.24E+05 1
2.00E+05
2.00E-02
4.48E+08
4.48E+07
4.30E+02
1.08E+04 2 3
1.00E+05
6.40E+08
6.40E+07
6.14E+02
1.54E+04 4
noise occu
1.00E-02
1.60E+08
1.60E+07
3.69E+02
9.22E+03 5
4.15E+02
1.04E+04
evt size L1-5
7kByte
evt size L0
66kByte
Present BaBar data
Similar in SuperB L1-L5
Paris, 16/02/09
M. Villa

8. Data transmission Option A: HDI with local rad-hard ram,optical links,
L1 handled in the HDI
Option B: HDI with line drivers, copper cables,
L1 handled outside detector
Memory buffers
And L1 logic
Buffers and
line drivers
optical/copper
Link
Optical Link
2.5 Gbit/s
FEC
ROM
Off detector
low rad area
Counting room
Std electronics
On detector
High rad area
Pro B: fewer rad-hard elements
few space required on HDI
full event readout (trigger)
commercial optical link only
Pro A: data flux reduced asap
shorter high load
connections
Paris, 16/02/09
M. Villa

9. EDRO Readout board
Front End Card used in Slim5 beam test (SVT par. II):
Main concept: flexibility at all levels
Mezzanines to decouple input/processing/output
Large FPGA
Several triggering schema
Slink
To DAQ
SuperB:
60 Mhz bus clocks
20 Gbit/s input rate
2.5 Gbit/s output rate
To be addressed
in the next versions
foreseen in 2009/10
Performances:
40 Mhz bus clocks
8 Gbit/s input rate
1 Gbit/s output rate
2.5 ME/s evaluated for L1
40 kHz DAQ
Data from
FE chips
4 Gbit/s
EPMC
Stratix
EPMC
TTCRQ
Not too far from SuperB numbers
Paris, 16/02/09
M. Villa

10. SVT in trigger and DAQ schemas
Current best FE chip candidates are data driven with an intrinsic time resolution of us
Interface between FE chips and SuperB trigger and DAQ will be provided by a board equipped with large FPGA, memory and optical links (i.e. flexible)
Consequences
SVT will fit both the fixed and variable L1 latency schemas
SVT readout time window of 1 us or larger will be handled in the HDI or off-detector electronics. Same for fixed or variable time window.
SVT might have the possibility to provide information on events before L1 trigger (L1-L5 best, L0 maybe).
SVT in trigger conceiveble.
Paris, 16/02/09
M. Villa

11. Conclusions Main SVT challenge: layer 0
rates, chips, data busses and data transmission
Current best FE chip candidates are data driven
Front End Card and/or HDIs with enough logic to fit different DAQ and L1 schemas
Trigger rate >150 kHz, time window >=1 us ✔
Data volume:
L0: 66 kB with 1 us time window and >5 safety factor
L1-L5: 7 kB with 1 us time window (Babar exp.)
SVT in trigger conceivable
SVT electronics R&D in 2009/10
Paris, 16/02/09
M. Villa