1. & pixel module interfaces On behalf of INFN Milano
Update on pixel bus
& pixel module interfaces
Mauro Citterio
On behalf of INFN Milano

2. Status of the “simplified bus”
The delivery of the prototype (1.8 x 11.2 cm) was delayed (!)
 now expected by Oct. 23, 2009
CERN Technology Stackup made of: Aluminum, polimide and glue
Various lines on the same structure to compare simulation and actual BUS
To test the technological limits in term of frequency (signal up to 160 MHz, 32bit BUS)
Four layers bus
2 planes (each 25 mm thick)  power and ground
2 signal layers
Signal lines with and without corners on the same layer
Signal lines on the two layers connected by means of minimum size vias
Lines with different overall lenghts, with and without bends
Striplines and microstrips, Differential lines
Min Pads/Vias 150/50 mm
Line widht: Min. ~ 75 mm, Max. 200 mm
Reduced from previous estimate

3. Bus Impedance simulated to 50 W
Data generated with CERN input
The dielectric thickness adjusted to increase Z
(~ 40 mm)
Line widht at the “nominal” minimum (~75 mm)
Line space will probably be reduced to ~ 50 mm
 it will not affect Z
 it will increases NEXT (~ 4.5 %)
Not minimum thickness
“Plane layers” thickness has been reduced from 50 mm to 25 mm
Aluminum signal lines has been also reduced from 13 mm to 10 mm
Total thickness of prototypes is expected to be ~ 160 mm

4. Updated estimate of final bus
Not an “enclosed stackup”:
Power planes must be on bottom
Maybe an additional power/ground plane will be necessary (it will means 90 mm more)
Signal lines are assumed to be microstrips
If 200 signal lines needed  Three signal planes (two horizontal, one vertical)
Using CERN "design rules"
Digital ground
Digital power supply
Horizontal signal lines
Vertical lines
Analogue power
Analogue ground
300 m for bonding on each bus side
Glue 5µ
Polyimide
15µ
290 µ
Polyimide
40µ
Aluminium 25µ
Aluminium 10µ
Aluminium 10µ

5. Signal Integrity Simulations with Hyperlinx
To study the performance of the Bus, we have simulated the signal propagation using XILINX VIRTEX-5 driver and receiver:
for which IBIS models are available
a driver/receiver similar to the one expected in the front-end electronics is used (LVCMOS12_S_8)
these block will be used in our test setup.
In the figure an “ideal” scenario is shown:
- Termination at the receiving end, based on the bus impedance
The signal has160 MHz frequency and 49 % duty cycle
The shape is “extracted” by means of the IBIS models
The driver sends out a 1.2 Volt signal at 8 mA

6. Signal Simulations: no termination
The bus is simulated by importing the stackup information:
-overall line + receiver are equivalent to a Cload ~ 12 pF
(Tr ~ 2 nsec)
No end of line termination used
The signal at the driver output is the “yellow” line
The signal at the receiver input is the “blue” line
The signal at the receiving end can still be read (logic level are matched), however the signal has very large distortion

7. Signal Simulations: series termination
In case that a line termination at the receiving end is not feasible, then the signal integrity can be recovered by adding a serie resistance at the receiving or driving (better result BUT difficult to implement) end of the bus.

8. Ongoing Activity Layout of a BUS for up to 3 front-end IC “FE 32x128”
- While awaiting for production completion the design of a “semi real” bus is in progress
- In this design the IC pad structure is going to be taken into account
- Decoupling capacitor will be mounted directly on the power plane  no via available to the the bus-top D 1 V
BUS width: 8.7 mm
300 mm
Space for signal layer: 7.5 mm D G N
Caps 0102 size
400 mm D 1 G N

9. Receiver +laser+VCSEL
HDI Design Progress
Only an hybrid (copper link + optical fibers) considered:
Hp: Not enough space for multiple optical links on the HDI near the detector
In this mixed-link solution, the HDI will drive a short copper link
Serializer capable of driving ~ 30 – 50 cm
Speed not exceeding 5 Gbit/s
The “transition card” (size ????) must be active
a “rad-tolerant” receiver not identified
IBL at CERN  receiver IC is going to be designed
A survey of commercial solution should be undertaken
An estimate of the radiation levels (worst case) would be useful
the survey undertaken on the Laser driver, VCSELs, fiber optic packages, etc. does not change
Optical link
2 x 5 Gbit/s
Transition Card:
Receiver +laser+VCSEL
Buffering
Modulations
Drivers
Cu bus
EDRO
Near detector
“soft” rad area
Counting
room
On detector
High rad area

10. Optical link
Even if an FPGA Control board based on Xilinx Virtex will be used for prototyping we have intiatiated a test campaign on “special components”
In particular we have started testing a Rad-hard serializer
“LOC1” developed in SOS by SMU Dallas (2.5 Gbps)
The IC is not really “user-friendly”  is an IC “in progress”
Electrical specification
Input power supply: 2.5V (Analog/Digital), 3.3V VCSEL
Power consumption ~200mW  high !!
Input data signals LVCMOS 2.5V
Reference clock 62.5MHz  optimized for LHC
20bit 8B/10B encoded input data
Some problems encountered (and confirmed by the designers)
The differential signal amplitude is about 240mV, measured by a differential probe. This is much lower than the 400 mV design spec.
The rise and fall times show a data pattern dependence. They are measured to be around 150ps. This is boarder line for 2.5 Gbps signal.
The reasons for the above problems are not completely known.
The device can be used for testing but we really need the LOC2
chip (expected by November 2009) with all problem solved, hopefully
Eye diagram of the Input 27-1 Pseudo random data.
UI = 400ps, for 2.5 Gbps.

11. Optical link Other component to be studied:
Other commercial interesting solutions:
Aeluros, Inc.: “standard 0.13 μm CMOS”
esilicon: “, 10.5 Gbps Serdes in 90 nm and 65 nm CMOS, TSMC”
Prism Circuits, Inc.
Fujitsu 65 nm HP process
Multi-rate 3.125Gb/s to Gb/s
Low jitter LC-PLL supports up to 8TX unidirectional lanes
1.25W per Gb/s (this is too good, need to check).
Other component to be studied:
Laser drivers: commercial (TX L2701and Micrel SY88992L) devices and GBT-LD  not yet started
Duplex LC package for housing two VCSEL and fibers  seems OK, follows CERN development

12. Test set-up … still under construction
Data generated via FPGA
Receiver + Glue Logic emulated via a custom made controller board
designed in collaboration with Sanitas EG
 should be completed by end of the year
Clock in
Serializer
Serializer
Other parts:
LINK: small progress on LOC
Serializers: components not yet received. Expected by end of October
Laser Driver: we are still deciding what to evaluate
PCB design: frozen until we can complete the test of other serializers
 goal: have a minimal system operating by end of the year
Output Drivers
Copper cable: variable lenght
Receiver and Laser Drivers
VCSEL double LC package

13. Conclusions Prototype bus: should be available soon
We are ready to start testing the electrical characteristics of the bus
Copper link: no progress
Optical link: some tests on LOC, more devices need to be tested
Test setup:
FPGA part is progressing well even if with some delays
Other parts: moves slowly, awaiting some crucuial part to take decisions on PCB design

14. SVT baseline configuration (1)
Layer Radius cm cm cm cm
to 12.7 cm
to 14.6 cm
Layer 0: Hybrid Pixels
Radius: ~ 1.5 cm
Module length: ~ 10 cm
Pixel Pitch: 50x50 mm2
Hit Rate: MHz/chip (safety > 5)
Module Rates: MHz
Link Bandwidth: 20 Gbps Full Rate (FE data push)
3 Gbps Triggered Rate
Power consumption: ~ 2 W/cm2 in the active area
~ 50 (mW/Gbps)/cm2 in HDI
Total material budget: ~ 1% X0
Si sensor + FE chips % X0
Al Bus + SMD comp % X0
Support & cooling ~ 0.3 % X0
Carbon Fiber Support
BUS
Half Module: 6 Sensors
HDI: ~ 13 x 70 mm2
Power/Signal
Data

15. SVT baseline configuration (2)
Layer Radius cm cm cm cm
to 12.7 cm
to 14.6 cm
External Layers: Double sided silicon detectors 300 um thick
Radius: BaBar radii for the 5 layers
Module length: similar to BaBar radii for the 5 layers
Structure: L1-L2-L3 barrel shape
L4-L5 arch shape
Extend coverage down to 300 mrad FW and BW
In BaBar it was 300 mrad FW and 520 mrad BW
Link Bandwidth: < 1 Gbps Full Rate (FE data push)
< 100 Mbps Triggered Rate
Power consumption: ~ 1 W/cm2 in HDI
Work ongoing using IC (FSSR2) that will require only minor modifications for SuperB
HDI design partly “inherited” by the layer 0 HDI design
HDI
Si Wafers
Data
Power/Signal
Front-end chips