1. Milano Activities: an update Mauro Citterio On behalf of INFN Milano

2. Summary Aluminum Bus Evaluation  measurements with improved accuracy
 design of a bus for “3-chip-assembly”
Rad-Hard SRAM
 on-going design and recent submission
 results from previous submission
Revision of the HDI
 what are the functionalities under study

3. Aluminum Bus Evaluation
Measurements on the 1st BUS prototype are on-going
 improved TDR measurements confirm a typical impedance of ~ 60 Ohm
 crosstalk is higher than estimated and can as high as ~10 %
 measurements performed on various samples with same results
Discussion on the stackup is still on going with CERN
simulation and actual BUS properties still do not agree
CERN or Milano will perform a “cut” of the BUS to verify layer thickness
frequency response (signal up to 200 MHz, on individual lines) are promising at full BUS lenght ~ 10 cm
Our goal was ~ 10 cm in BUS lenght. indeed
1st layer signal traces
“cover layer”
ground plane
2nd layer signal traces
155 µ
Glue 5µ - er = 4.5
Polyimide 40µ - er = 3.5
Aluminium 25µ
Aluminium 10µ
Polyimide 20µ - er = 3.5

4. Impedance Measurements
End of a probe
(un-terminated)
Probe contact (negligible
parasitic inductance)
50 ohm injection line
Trace impedance
Impedance measurement for 6 “identical” traces
The positive slope measures the trace resistance
Trace impedance is > 60 Ohm
Traces are not homegenuos in impedance

5. Signal Integrity Measurements
Trace lenghts ~ 10 cm:
- Termination at the receiving end is 50 Ohm
The signal has 200 MHz frequency and 50 % duty cycle, 1 Volt amplitude
Reference line (60 Ohm) is a PCB trace used for calibration
Set-up for multiple trace injection is being put together

6. Crosstalk measurements
From Simulation:
- Hp: “one” aggressor and one victim nearby.
- Signal on victim is approximately 30 mV at its peak
- Signal on victim is mostly due to the nearby aggressors
NEXT ~ 3 %
From Measurement:
- Signal on victim is indeed due to nearby aggressors
- Lines are with via between two layers
NEXT ~ 10 %

7. Bus for a 3-chip Assembly
Layout of a BUS for up to 3 front-end IC “FE 32x128”
- Bus widht: 8.7 mm
- Signal trace layer widht: 7.5 mm
- Bus length ~ 6.5 cm
Issues accepted by CERN:
- “Area opening” of 300x500 mm possible on power planes to allow decoupling cap mounting. The size of the openings is the “best results” on test structures
- The stackup (layer and dielectric thickness) will be similar to the one used in the prototype bus. However multiple thin polyimide layers will be used to get “thick insulating” layers (to use same brand material everywhere)
Detailed design NOT started

8. Radiation hardened SRAM (A. Stabile, V. Liberali)
Radiation hardness (rad-hard) is achieved by means of design techniques
Rad-hard techniques are used at various levels of representation:
system level;
architecture level;
circuit level;
layout level.
Fabrication process: 180 nm standard CMOS
good trade-off between cumulative effects and single event effects.

9. Design of a rad-hard SRAM cell
Edgeless nMOS transistors to mitigate cumulative effects
“Fringe” capacitor to mitigate single events
Large number of bulk/n-well contacts to mitigate latch-up

10. SRAM cells comparison
We have designed three different rad-hard SRAM cells:
H-cell: Good level of radiation hardening
Cumulative effect: up to 10 Mrad of dose
Cell area: 16 µm2
S-cell: Medium level of radiation hardening
Cumulative effect: up to 2-3 Mrad of dose (estimated)
Cell area: 13 µm2
M-cell: Rad tolerant cell
Cumulative effect: up to 1 Mrad (estimated)
Cell area: 9 µm2
180 nm standard (non rad-hard) SRAM area: 7 µm2

11. Cell layouts
H-cell S-cell M-cell

12. RC7C512RHH 512 kbit SRAM Based on H-cells
Tested up to 10 Mrad of total dose
Access times range from 10 to 20 ns
Fabricated in 2009 by X-FAB (Sarawak)

13. RC7C512RHS 512 kbit SRAM Based on S-cells
We have estimated a rad-hard level up to 2-3 Mrad of dose
Access times range from 7 to 16 ns
Submitted for prototyping to X-FAB (Sarawak), Feb. 2010

14. Power consumption (1/2)
Power consumption strongly depends on total dose received
Power consumption in memories based on H-cells increases of few microampere, which is only due to parasitic leakage currents generated by I/O pads
Pre radiation power consumption:

15. Power consumption (2/2)

16. Receiver + optical link
Revision of the HDI
New Baseline will not necessarily require that all data will be transferred to the transition card
the HDI could/should act as a data buffer awaiting for trigger, if necessary
The SRAM project will provide guidelines
The HDI will drive a short copper link (up to 50 cm)
How many copper lines are needed is under study
The line drivers will be preceded by a “formatting logic”
The “transition card” will do the transition between copper and fiber using the optical link suggested by Aloisio
Transition Card:
Receiver + optical link
Optical link
~ 1 Gbit/s
Buffering
Modulations
Drivers
Cu “bus” ~ 50 cm
Power lines
EDRO
Near detector
“medium” rad area
(10 krad/yr)
Counting
room
On detector
High rad area (15 Mrad/yr)