1. Update on the activities in Milano
SuperB Meeting: SVT Parallel Session
Update on the activities in Milano
M. Citterio
on behalf of INFN and University of Milan

2. Bus / Fan-out status (1 of 2)
Production of BUS not yet started
The layout has been updated once more to correct some ‘possible’ production difficulties
Opening on the ground/power planes have been enlarged and re-positionated
Bonding Scheme (Bus to Sensor and FE chip) has been affected and it’s ready to be reviewed with Pisa
The sign-off meeting is planned for next week
Production will start immediately after that (4-5 weeks)
CERN under pression to complete IBL Flex (final design review will be held tomorrow)
Queen Mary Univ., Sep. 2011
Mauro Citterio

3. Bonding Scheme Some “juggling” required …. It could be
feasible at the prototype phase …
Queen Mary Univ., Sep. 2011
Mauro Citterio

4. Bus / Fan-out status (2 of 2)
Search of commercial partner for FAN-OUT (layer 0) is still on going  in May two possible firms have shown interest
One firm is in France, while the other is in Italy
Both company will start from a thin commercial Copper/Kapton tape (5 um / 25 um) and pattern the layout by etching
Experience only for lines/space resolution of 50/50 um (twice the baseline for striplets) over 10 cm lenght as a maximum
UPDATES:
The French firm will not be ready for a trial circuit for at least another year
The Italian firm is willingly to build a prototype first quarter of 2012
Initiated new contacts (USA firm)
Queen Mary Univ., Sep. 2011
Mauro Citterio

5. Example Attribute Standard HDI: Dense HDI: LCP HDI: PTFE
(Epoxy Glass or Polyimide)
HDI: Dense
(Particle Filled Epoxy)
HDI: LCP
(liquid crystal polymer)
HDI: PTFE
(PTFE)
Line width
75 microns
25 microns
37.5 microns
Line space
33 microns
Via type
mechanical
laser
Laser
Via diameter
200 microns
50 microns
Stacked vias
Build up only
In 2010
Capture pad diameter
400 microns
100 microns
110 microns
Surface finish
E-less Ni / I Au, ENEPIG
Same
Solder mask
yes no
Thickness
<1mm mm
0.5mm
Layers 10 12
4, 6 in 1st article 11
Queen Mary Univ., Sep. 2011
Mauro Citterio

6. SuperB HDI (1 of 2) AUREL “ moderate” INTEREST
Technology for SuperB HDI: AlN thick film hybrid
Irregula shape is not an Issue
Detector fan-out is glued on the hybrid edge and chips inputs are wire bonded to the fan-out.
Five conductive layers (3 power/ground layers, 2 for signal)
However, each additional signal layer for HDI-0 will “degrade” planarity and line resolution
New layout rules
- layer thickness ~ 65 mm (5% tolerance *)
(15 um conductor and 50 mm dielectric)
Thickness usually decreases during oven curing
Line size/space: inner signal layer >100/100 um (typical 150/150 um), 200/200 um TOP layer
Pads 200 x 200 um*2
Vias 200 um, space between via ~ 250 um
AUREL “ moderate”
INTEREST

7. SuperB HDI (2 of 2) AUREL INTEREST Some Open Issues
No systematic impedance control
Limited possibility to change the dielectric layer thickness with the standard process.
By print screening company prefers a standard “3 pass” procedure  dielectric thickness ~ 50 um.
Some avenue to be pursued:
evaluate the usage of dielectric in tape (predefined thickness)  limited choices of thick film materials compatible with AlN
Mix AlN and Al2O3 materials. Possible after the first power/ground layer.
Clock lines were “qualified” by try and test in Babar
Difficult prediction of Z  dielectric constant usually not well specified by material manufacturer (ex. in next slide)
Some prototypes were produced to master the technology
Same approach to be pursued.
Of particular interest is the implementation of differential lines (digital signal ~ MHz)
Prototype: small substrate (length counts), two layer (plane and one signal), array of lines of minimum size (number to be defined)
AUREL INTEREST

8. SuperB HDI Impedance Test Structures
AUREL is willingly to produce a ‘small’ set of substrates to measure yield and characteristics of various
Layout is simple, parallel lines with lenght similar to HDI lenght
We are trying to organize ourselves to make signal integrity test at AUREL production site (Modigliana)
Goal is to assess the best solution
Cost is moderate but not zero  it will be discussed next week
Queen Mary Univ., Sep. 2011
Mauro Citterio

9. Low Speed / Low Power Serializer
The block schematic of the SMU LOC1 shows that the typical power of the chip (~ 500 mW at 5 Gbps) has a substantial contribution coming from the PLL circuit.
A “Tunable” Serializer (data rate from 2.5 to 5 Gbps) can be obtained by changing the PLL.
The goal is to reduce the power to ~ 250 mW at 2. 5 Gbps
Simulation results indicate that:
Updates:
We have intensified the discussion with SMU group.
We need soon:
A choice of the technology (0.25 um or the new 0.18 um Silicon on Sapphire available 2nd quarter of 2012? )
Is SOS the right choice (only one source ….)
We need a set of specifications/data protocol
The SMU is eager to start.
LOCs1 (mW)
low power design
CML Driver  96
50%
PLL
173
80%
Others
187
30%
Queen Mary Univ., Sep. 2011
Mauro Citterio