1. Plans for pixel module integration electronics
Mauro Citterio
On behalf of INFN Milano

2. SVT System Integration
Baseline:
SuperB SVT  similar to BaBar SVT + Layer 0
Layer 0 technology to be chosen between maps, striplets or thin pixels
Each SVT layer is built of indepedent “modules” (52+8)
One module is divided in two independent “half modules”
Each half modules contains several “units”:
Sensor
Front-end chips
Interfaces (BUS and HDI) with power/signal input and data output link
Layer 0
Required for
System Integration

3. Preliminary Bus Design
Baseline:
Layer 0 BUS is the most challenging  Example shown is for MAPS
Highest signal trace density  ~ 200 signal lines
Minimum thickness  goal thickness ~ 220 mm
Sensor/readout  wire bonded to BUS
Carbon Fiber Support
BUS
Half Module: 6 MAPS

4. Preliminary Bus Design
Baseline:
Basic idea is to “revise” and redesign the ALICE multilayer bus built by CERN PCB shop
Stackup: Aluminum and kapton (various available thicknesses)
4 power planes + 2 (3) signal layers + vias
Min line widht space ~ 75 mm
Min line space ~ 50 mm
Built by “sequential lamination” after a layout optimization
Aluminum thickness ~ 25 mm for power planes, ~ 5-10 mms for signal layers
Dielectrics (polyimide + glue) ~ 20 mm
Min Pads/Vias 150/50 mm

5. Preliminary Bus Design
Half Module Prototype :
An Half Module (as sketched in the figure) will need a BUS with
widht ~ 12.6 mm and lenght ~ mm
Analog, Digital Power and 2 Returns on two side of the BUS
(interdigitation at ~ 1mm pitch, 300 mm width at each side)
Each MAPS will probably have a 30 bit data bus + auxiliary lines
 total number of traces ~ 200
Line pitch on signal layer  one layer: 60 mm pitch
 two layers: 120 mm pitch (!!)
Adding a layer means: 10 mm of aluminum + 20 mm of dielectric

6. Preliminary Bus Design
Not an “enclosed stackup”:
Power plane must be on bottom
Signal lines are microstrip instead of stripline
Better for speed, “high” impedance. Lines are accessible
Worse for far-end crosstalk and EMC
Using CERN design rules
265 µ
Glue 5µ
Polyimide
15µ
Aluminium 25µ
Aluminium 10µ
Digital ground
Digital power supply
Horizontal signal lines
Vertical lines
Analogue power
Analogue ground
300 m for bonding on each bus side

7. Preliminary Bus Design
Electrical parameters:
Each APSEL chip bus requieres
30 output lines ~ 160 MHz ( Rise time: tr ~ 1.5 nsec)
Each half module needs also
10+10 I/O control signal
(160 MHz OutClock, all other at ~ 60 MHz)
 What are the expected frequency performance for a “fine line/pitch” bus?
For a 70 mm bus  propagation time tpd ~ 0.51 nsec (kapton er ~ 3.5)
Propagation time does not depend from bus geometry (i.e “fine” lines)
To avoid reflections
Unconditional 2 tpd < 0.1 tr  tr > 10.2 nsec (< 16 MHz)
Conditional tpd < 0.3 tr  tr > 1.7 nsec (!!!)

8. Preliminary Bus Design
First goal to be achieved is the minimization of reflection:
Characterization of the signals by simulation and by direct measurements
- at the nominal frequency of operation (~160 MHz) dissipative effects should be still negligible
- some concern from the “quality” of the aluminum deposition
- it could be necessary to add ~ 1 mm copper plating
Impedance matching between BUS and driver/receiver
- “End point” line termination should be sufficient (to be verified)
- BUS lines impedance calculated with field solver
- stack- up not homogenious
- Dual Microstrips (+ Offset)
 preliminary simulation (w= 75 mm, w/h ~ 3, t << w) Z0 ~ 30 W (Z0 spread +/- 2 W)

9. Preliminary Bus Design
Other element under analysis is NEXT:
Line separation is should be far from Backward Crosstalk Coefficient (BCC) saturation (w= 75 mm, s/h ~ 4  s= 100 mm)  BBC ~ 3-5 %
NEXT has a weakly dependence from BUS impedence
FEXT in microstrip:
“nonhomogenious” lines means crosstalk
 difficult to have an accurate simulation without real measurement
 BUS layers are pressed and glued together  rough surfaces
Termination mismatch always present (example : corner, via/pad)
Both NEXT and FEXT need to be measured accurately

10. Still to be defined Unspecified parameters
For a layout, PADs position on chip must be defined
Evaluation of clock skew
No “decoupling” on the BUS
What is the tolerable Jitter
......
Power distribution:
What is the tolerable drop on the power planes?
Can we use a single power plane split in two  substantial reduction in bus thichness (~ 70 mm)

11. Ongoing Actions Two layer test BUS  layout in progress
To be Build at CERN (Rui De Oliveira)
To measure most of the “critical parameters”
Various pitches will be used (in a testing matrix)
Various “shapes-corners” will be used
Comparison between measurement and simulation
Using HSPICE e Hyperlinx
Improvement of stack-up details.
Single ended vs differential lines
Check of Via modelling
 Parameter adjustment (No. of lines, widht, etc. ) to reach the “nominal” bandwidth

12. Hybrid Design (first solution)
Structures: From Mauro Villa’s talk
Hybrid Dimension ~ 13 mm x mm x H mm
Some space need to connect hybrid and BUS ( < 1 cm2 )
No space for FPGAs in the final hybrid
Xilinx Virtex family or Altera Stratix Gx could be used for prototyping
(> 300 user I/O pins, RAM, fast transceiver up to 6 Gbps) ( goal 3 Gbps)
SRAM rad-tolerant memory under development (~ 0.5 MB), ASICs for logic + serializer
Small space for the optical link  difficult !!
To DAQ
EDRO
EPMC
EPMC
Optical Fiber
60/80 MHz

13. Hybrid Design (Second Option)
Structure:
No GBT-tied design
Optical links 2.5 Gbit/s from detector to counting room
IN/OUT connection
 For the input BUS (< 1 cm2 )
 For the COPPER output BUS (???? cm2)
Hp. All data out
Buffering
Modulations
Drivers
Cu bus
< 20 Gbit/s
Optical link
2.5 Gbit/s
Edro
like
ROM
Off detector
low rad area
Counting
room
On detector
High rad area

14. Hybrid Design (Copper Link)
Copper Interconnects:
For distances less than 20 m, copper is viable alternative to optical fiber
Several standard-setting bodies are involved in developing 10Gbit/s fabrics for various high-performance applications.
The industry standards have all created bus structures based on high-speed lanes or channels, using 2.5 to Gbits/s per lane
[Ex. 10G Ethernet (IEEE 802.3ak – CX4), InfiniBand, 10G Fibre
Channel, Serial Attached SCSI (SAS), and Serial ATA2 (sATA-2)]
Rather than attempting to push all the data down a single 10-Gbit/s pipe, copper interconnects use lanes of differential signals, each operating at around 3 Gbits/s in parallel.
 A lane comprises two differential pairs one pair for transmission and the other for reception
 Each differential pair is isolated by ground pins that effectively isolate each signal pair.
Cable manufacturers have successfully developed copper cables capable of accommodating signal speeds up to 5 Gbits/s.

15. Hybrid Design (Nuova Ipotesi !)
A copper connector series such as Fujitsu's microGiGaCN includes 4X and 12X connectors
(OK for the EDRO board, careful layout required on the Hybrid)
Different cable assemblies are required for various reaches
 Assuming a speed of Gbits/s, a 24-AWG cable assembly with no equalization circuitry is suitable for distances of 4 to 5 m in a bidirectional differential mode ( < 1 mm2)
The length of the link can be extended using equalization circuitry and or preconditioning the signal before it is launched on the transmit side
BUT: - at these speed we are talking “state of the art chipset”
- we need rad-hard chipset to feed the cooper link