ECAL front-end electronic status CALICE meeting, Oct, 12th Christophe de La Taille Gisèle Martin Julien Fleury

Plan Quick physic prototype electronic news R&D on front-end chip : ILC_PHY4 ILC_PHY4 features ILC_PHY4 control ADC control Slow control Planning Front-end board ILC_FEV4 to read ILC_PHY4

Physic prototype news

Physic prototype news Supply boards for physic prototype : Produced Tested : 60 needed, 67 good over 70 produced Features : prevent voltage surge on front-end supply Regulate front-end supply Filter high-voltage supply New power supplies in hand 3* Lambda 8V / 80Amps GPIB for slow control Will pass DESY safety control

Physic prototype news (2) Spare building : 10 full, 5 left and 5 right PCBs Packaging of 1600 FLC_PHY3 Components provisioning done PCBs in hand Assembling & test in Nov-Dec 2005 Ready for collaboration beginning 2006

ILC_PHY4

ILC_PHY4 features 18 channels 2 analogue multiplexers 181 Multi gain charge preamp (167mV/pC 2.5V/pC) Dual shaper gain 1&10 2 track and hold Switchable calibration injection capacitance 2 analogue multiplexers 181 One for gain 1 and one for gain 10 The two MUX output are MUX to a single output 1 ADC – 12 bit / 1MSPS – IP from AMS (founder) An internal bias device including : Internal decoupling on current sources Idle mode on whole analogue parts of the chip

ILC_PHY4 control Analogue part compatible with FLC_PHY3 Hold read Q_R Rst_R CK_R read GSW Q_R G1 Ch.1 G10 Ch.2 Ch.3 Hold 1 2 3 16 17 18 OUT Ch.16 Ch.17 G1 Ch.0

ADC control Input : Output : Clock (LVDS) Convert (CMOS) Launch a conversion Reset (CMOS) Output : Data out (LVDS) Serial output Busy (CMOS) High when converting Data of sample N-1 will be provided in serial while sample N will be converted A conversion takes 20 rising clock A data serializing takes 13 rising clock

Slow control Preamp gain : 4 bits 120 MIP 2000 MIP Switch configuration Feedback Capacitance Gain Capa SW0=3.2pF Capa SW1=1.6pF Capa SW2=0.8pF Capa SW3=0.4pF OFF 0pF Open loop ON 0.4pF 2.5V/pC 0.8pF 1.25V/pC 1.2pF 833mV/pC 1.6pF 625mV/pC 2pF 500mV/pC 2.4pF 417mV/pC 2.8pF 357mV/pC 3.2pF 312mV/pC 3.6pF 278mV/pC 4pF 250mV/pC 4.4pF 227mV/pC 4.8pF 208mV/pC 5.2pF 192mV/pC 5.6pF 178mV/pC 6pF 167mV/pC 120 MIP 2000 MIP

Slow control (2) Preamp speed (3 bits) ADC self power down control – 1 bit Current doubling – 1 bit Not really a slow control : Output gain (1 or 10) – 1 bit Idle mode (power on or off) – 1 bit

ILC_PHY4 planning Chip will be back in october Testboard is assembled this week Tests to be performed in November Results for beginning 2006

Test beam with that chip necessary ILC_PHY4 goals Test 0.35 technology in beam Test external-bias-free front-end Test power pulsing in test beam Test digital DAQ Test beam with that chip necessary

Design of ILC_FEV4 FLC_FEV1 FLC_FEV2 ILC_FEV3

Design of ILC_FEV4 (2) Front-End Board V4 ILC_PHY4 inside Mechanically compatible with physic prototype Need of a mini DAQ to read out 1 or 2 of these PCBs Design of ILC_FEV4 in strong interaction with DAQ Expected before spring 2006

Design of ILC_FEV4 (3) Chip in the detector Thickness Ultra-thin PCB Chip burried in PCB 1750µm diodes+ FE electronic PCB (600µm) Wafer (500µm) FE chip (1mm)

The future : where do we go ?

What is missing in ILC_PHY4 Auto-trigger Fast shaper Discriminator High precision pulse generator for calibration 16 bits DAC RF switch Voltage reference in the chip Bandgap Digital state machine for subadressing Digital and analogue memory Bunch crossing ID counter Subadress machine

What is missing in ILC_FEV4 Stitchable PCBs (no room for cables) 1.5m Glue ? Solder ? PCB type 1 PCB type 3 PCB type 2

Conclusion ILC_PHY4 : a main step : First fully functionnal multi channel FE chip in 0.35µ Many features : ADC, Idle mode, self-biased Many measurements planned on ILC_PHY4 0.35µ techno in test beam Full detector chain in test beam with power pulsing