2. Electronics for the E-CAL physics prototype
CALICE COLLABORATION
Electronics
for the E-CAL
physics prototype
Julien Fleury, LAL, Orsay

3. Table of content Schedule About the Opera chip
What ’s up with the new FLC_PHY1 chip ?
The physics prototype first PCB
Conclusion

4. What have been done since feb. 20th
Schedule
What have been done since feb. 20th
Two axis :
Physics prototype PCB
Very front end chip
First PCB : 3 active wafers
working on dimension issues
design of the PCB
Still to be done :
Working on connector issues
Working on I/O issues
Test of opera chip
Simulation of FLC_PHY1 chip
Layout of FLC_PHY1

5. About the opera chip Reminder How does it work ? On chip Detector
DC block
Detector
Charge preamp
shaper
Track & hold
Amp
Vdc = -200V
OPA

6. About the opera chip Measurement About 1.5% non-linearity
3V dynamic range
430 fC (68 MIP)
Noise below 1000 electrons
(i.e. 0,16 fC or 0,023 MIP)
@180 ns peaking time

7. The new FLC_PHY1 chip Change & improvment OPERA HPD (meas.)
FLC_PHY1 (sim.)
18 inputs/18 outputs/
1 MUX output
16 inputs/1 MUX output/2 test channels
4.2 pC max input charge
(650 MIP)
430fC max input charge
(68 MIP)
2.8V dynamic range
below 1% non-linearity
3V dynamic range
about 1.5% non-linearity

8. The new FLC_PHY1 chip FLC_PHY1 pin out Inputs Outputs MUX output
Vbiasm_pa
Out 0
Out 1
Out 2
Out 3
Out 4
Out 6
Out 5
Out 8
Out 10
Out 9
Out 7
Out 12
Out 13
Out 15
Out 14
Out 11
Vdda
In 0
Vbiasi_pa
Vb_casc
V_rf Vf
Vbiaso_pa
Vbiasi_sh
Vbiaso_sh H R
Vss
Vbias_cell
In 16
Ck_R
In 1
In 2
In 3
In 4
In 5
In 6
In 7
In 8
In 9
In 10
In 11
In 12
In 15
In 14
In 13
SW1
In 17
Vdd
SW2
Out_pa
Q_R
Bias_buf
Out
Bias_out
Out17
Out 16 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 17 18 19 20 21 24 22 23 31 30 29 28 27 26 25 40 39 38 32 37 36 35 34 33 47 46 45 44 43 42 41 51 50 49 48 56 57 58 59 60 61 62 63 64 55 54 53 52
FLC_PHY1
TPQFP 64 package
Rst_R
Package:
Plastic TQFP(1100Eu/chip!)
Ceramic TQFP (To be estimated)
Inputs
Outputs
MUX output

9. The new FLC_PHY1 chip FLC_PHY1 simulation Transcient analysis
Peaking time : 180 ns
Non linearity below 1%
up to 650MIP (4.3pC)

10. The first physics proto PCB
Global Design
3 active wafers
36 cells per wafer
3x36=108 channels
108/18=6 FLC_PHY1 chips
Wafer 2 3
Fake
wafer
VFE 1
370mm
62mm
31mm
10 layers PCB
built-in calibration capacitors

11. The aluminium sheet carries
The first physics proto PCB
PIN diode
10mm 2 6
62mm
62mm
1 wafer
Cell footprint
Aluminium sheet
Diode bias
Sig. readout
PCB
Wafers
The aluminium sheet carries
the ground to the cells
Cell circuit

12. The first physics proto PCB Calibration
Bias (-200V)
6 calibration circuits
each working on 18 cells
Detector
VFE Chip
Icalib L R
Cinjection
Calibration
timing

13. The first physics proto PCB Calibration
Cell footprint
Via
Top Layer
Layer C2
To signal
layer
10 layers PCB
Layer C2 Calibration
Injection capacitor

14. The first physics proto PCB Input/output
Digital sample and hold timing signal
Digital multiplex clock signal
Digital shift register reset
Digital shift register input
Analog calibration voltage (current) level
6 digital calibration timing OR
1 timing and 3 (4) bit cal. channel selection
OUTPUT
6 Analog multiplexed data signals
(108 Analog data signals?) -> connector issues
6 digital shift register output

15. Conclusion What to do know Before summer Build the first PCB
Design and build a test board for FLC_PHY1
Around September
Receive and test FLC_PHY1
Build the first physics prototype card
Test that first card

16. Questions