FEE Electronics progress PCB layout progress VHDL progress in TBU Prototype fixture for software 9th June 2009

PCB Layout Progress 9th June 2009 Complete memory  95% complete – power and decoupling Gbit Ethernet.  90% complete – power and decoupling ADC output signals to the FPGA.  100% complete Discriminator signal connections to the FPGA  100% complete Mezzanine connector signal definition   60% complete Clock distribution to the ADCs  100% complete Power supply blocks and delivery planes. FPGA configuration memory. Temperature sensors, RS232, LEDs etc. April 30 th : 49% signals routedJune 9 th : 77% signals routed

PCB layout targets June 30 th : –Complete routing and layout. –Submit to manufacturer for validation and quote. –Submit to assembler for evaluation of assembly and final parts purchase. July 7 th : –Complete engineering review. July14th : –Submit to pcb manufacturer and assembler. August 17 th : –Assembled FEE64 delivered. 9th June 2009

Collaboration with Detector Systems Development Group of TBU. (Technology Business Unit ) Currently : –Gbit data rate from memory on the devkit => 240Mbit/sec. –System boots with fallback to golden copy. –Pin allocation of FEE64 memory and Gbit signals checked. Next steps : –Create a DMA peripheral and check performance. –Create a memory test and configuration system. 9th June 2009

Prototype fixture for software development Pin out and advice provided by Steve Thomas. Fixture will allow communications between the ASIC and Linux to be developed. Mux readout logic VHDL can also be developed. Design and manufacture of fixture in progress in DL electronic workshops. Delivery mid June. 9th June 2009 Fixture comprises a ZIF socket on a pcb designed to mount a packaged ASIC onto an ML507 FPGA development board.